196-pin
Abstract: DSP56300 EB360
Text: Freescale Semiconductor Engineering Bulletin EB360 Rev. 1, 10/2005 Mechanical Differences Between the 196-pin MAP-BGA and 196-pin PBGA Packages This document describes the differences between the 196-pin Mold Array Process-Ball Grid Array MAP-BGA and the 196pin Plastic Ball Grid Array (PBGA) packages. The MAP - BGA
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EB360
196-pin
196-pin
196pin
DSP56300
EB360
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Untitled
Abstract: No abstract text available
Text: DS92LV1260 DS92LV1260 Six Channel 10 Bit BLVDS Deserializer Literature Number: SNLS134E DS92LV1260 Six Channel 10 Bit BLVDS Deserializer General Description Features The DS92LV1260 integrates six deserializer devices into a single chip. The chip uses a 0.25u CMOS process technology. The DS92LV1260 can simultaneously deserialize up to
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DS92LV1260
DS92LV1260
SNLS134E
DS92LV1021
DS92LV1023
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Untitled
Abstract: No abstract text available
Text: SMJ320C30 DIGITAL SIGNAL PROCESSOR SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004 2 D −55°C to 125°C Operating Temperature D D D D D D D D D D D Range, QML Processing Processed to MIL-PRF-38535 QML Performance − SMJ320C30-40 (50-ns Cycle) 40 MFLOPS
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SMJ320C30
SGUS014H
MIL-PRF-38535
SMJ320C30-40
50-ns
SMJ320C30-50
40-ns
32-Bit
64-Word
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Untitled
Abstract: No abstract text available
Text: BCM8228 VARIRATE MULTIRATE TRANSCEIVER WITH SONET RATE ADAPTATION AND PERFORMANCE MONITORING SUMMARY OF BENEFITS FEATURES • Highly-integrated rate-adaptation device that maps a single STS-3/ STM-1 or a single STS-12/STM-4 stream into STS-48/STM-16 frames.
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BCM8228
STS-12/STM-4
STS-48/STM-16
155-Mbps/622Mbps/2
488-Gbps
STS-12/STM-4.
STS-48/
STM-16
BCM8228
196-pin
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TQFP 144 PACKAGE Freescale
Abstract: DSP56309 DSP56302 EB346 SC10 SC11 SC12 cpcap
Text: Freescale Semiconductor Engineering Bulletin EB346 Rev. 3, 10/2005 Functional Differences Between DSP56302 and DSP56309 formerly DSP56302A To meet the increasing demands for higher performance and lower power consumption, an advanced DSP56302 has been designed; it is was formerly known as DSP302A; it is now
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EB346
DSP56302
DSP56309
DSP56302A)
DSP302A;
DSP56309.
DSP56302.
TQFP 144 PACKAGE Freescale
DSP56309
EB346
SC10
SC11
SC12
cpcap
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XC56303PV80
Abstract: pcr1a XC56303PV66 DSP56000 DSP56300 DSP56303 HA10 msc 1697 XC56303GC100 MCE Semiconductor
Text: MOTOROLA Order this document by: DSP56303/D SEMICONDUCTOR TECHNICAL DATA DSP56303 Advance Information 24-BIT GENERAL PURPOSE DIGITAL SIGNAL PROCESSOR The DSP56303 is a member of the DSP56300 core family of programmable CMOS Digital Signal Processors DSPs . This family uses a high performance, single-clock-cycle-per-instruction
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DSP56303/D
DSP56303
24-BIT
DSP56303
DSP56300
DSP56000
DSP56300
XC56303PV80
pcr1a
XC56303PV66
HA10
msc 1697
XC56303GC100
MCE Semiconductor
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Untitled
Abstract: No abstract text available
Text: SMJ320C30 DIGITAL SIGNAL PROCESSOR SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004 2 D −55°C to 125°C Operating Temperature D D D D D D D D D D D Range, QML Processing Processed to MIL-PRF-38535 QML Performance − SMJ320C30-40 (50-ns Cycle) 40 MFLOPS
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SMJ320C30
SGUS014H
MIL-PRF-38535
SMJ320C30-40
50-ns
SMJ320C30-50
40-ns
32-Bit
64-Word
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Untitled
Abstract: No abstract text available
Text: Freescale Semiconductor Technical Data DSP56311 Rev. 8, 2/2005 DSP56311 24-Bit Digital Signal Processor 3 16 6 6 Memory Expansion Area EFCOP Peripheral Expansion Area Address Generation Unit Six Channel DMA Unit X Data RAM 48 K x 24 bits YAB XAB PAB DAB Y Data
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DSP56311
24-Bit
24-Bit
DSP56300
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Untitled
Abstract: No abstract text available
Text: SMJ320C30 DIGITAL SIGNAL PROCESSOR SGUS014H - FEBRUARY 1991 - REVISED JUNE 2004 2 D -55°C to 125°C Operating Temperature D Two 32-Bit External Ports D D D D D D D D D D D D Range, QML Processing Processed to MIL-PRF-38535 QML Performance - SMJ320C30-40 (50-ns Cycle)
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SMJ320C30
SGUS014H
32-Bit
MIL-PRF-38535
SMJ320C30-40
50-ns
SMJ320C30-50
40-ns
64-Word
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Untitled
Abstract: No abstract text available
Text: SMJ320C30 DIGITAL SIGNAL PROCESSOR SGUS014H - FEBRUARY 1991 - REVISED JUNE 2004 2 D -55°C to 125°C Operating Temperature D Two 32-Bit External Ports D D D D D D D D D D D D Range, QML Processing Processed to MIL-PRF-38535 QML Performance - SMJ320C30-40 (50-ns Cycle)
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SMJ320C30
SGUS014H
32-Bit
MIL-PRF-38535
SMJ320C30-40
50-ns
SMJ320C30-50
40-ns
64-Word
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Untitled
Abstract: No abstract text available
Text: SMJ320C30 DIGITAL SIGNAL PROCESSOR SGUS014H - FEBRUARY 1991 - REVISED JUNE 2004 2 D -55°C to 125°C Operating Temperature D Two 32-Bit External Ports D D D D D D D D D D D D Range, QML Processing Processed to MIL-PRF-38535 QML Performance - SMJ320C30-40 (50-ns Cycle)
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SMJ320C30
SGUS014H
32-Bit
MIL-PRF-38535
SMJ320C30-40
50-ns
SMJ320C30-50
40-ns
64-Word
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TMS320C5000
Abstract: XDS100 TMS320C5514
Text: TMS320C5514 SPRS646D – AUGUST 2010 – REVISED APRIL 2011 www.ti.com TMS320C5514 Fixed-Point Digital Signal Processor Check for Samples: TMS320C5514 1 Fixed-Point Digital Signal Processor 1.1 Features 12 • High-Performance, Low-Power, TMS320C55x Fixed-Point Digital Signal Processor
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TMS320C5514
SPRS646D
TMS320C5514
TMS320C55xTM
33-ns
120-MHz
TMS320C5000
XDS100
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Untitled
Abstract: No abstract text available
Text: TMS320C5515 SPRS645D – AUGUST 2010 – REVISED APRIL 2011 www.ti.com TMS320C5515 Fixed-Point Digital Signal Processor Check for Samples: TMS320C5515 1 Fixed-Point Digital Signal Processor 1.1 Features 12 • High-Performance, Low-Power, TMS320C55x Fixed-Point Digital Signal Processor
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TMS320C5515
SPRS645D
TMS320C5515
10-Bit
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Untitled
Abstract: No abstract text available
Text: 89HPES8T5A Data Sheet 8-Lane 5-Port PCI Express Switch ® Device Overview u The 89HPES8T5A is a member of IDT’s PRECISE family of PCI Express switching solutions. The PES8T5A is an 8-lane, 5-port peripheral chip that performs PCI Express Base switching. It provides connectivity and switching functions between a PCI Express upstream port and
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89HPES8T5A
89HPES8T5A
BCG196
196-ball
89HPES8T5AZBBC
196-pin
BC196
89HPES8T5AZBBCG
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DSP56000
Abstract: DSP56300 DSP56L307
Text: MOTOROLA Order Number: DSP56L307P/D Rev. 1, 3/2001 Semiconductor Products Sector Product Brief DSP56L307 24-BIT DIGITAL SIGNAL PROCESSOR The Motorola DSP56L307, a member of the DSP56300 family of programmable Digital Signal Processors DSPs , supports network applications with general filtering operations. The on-chip Enhanced Filter
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DSP56L307P/D
DSP56L307
24-BIT
DSP56L307,
DSP56300
DSP56L307
DSP56000
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circuit card assy input filter for miller 200 Dx
Abstract: 64 point radix 2 FFT LM318 list DSP101 74AS20 TTL radix-4 DIT FFT C code TLC32040C TMS320 TMS320C31 TMS320C32
Text: TMS320C3x GeneralĆPurpose Applications User’s Guide 1998 Digital Signal Processing Solutions Printed in U.S.A., January 1998 SDS SPRU194 TMS320C3x General-Purpose Applications User’s Guide Literature Number: SPRU194 January 1998 Printed on Recycled Paper
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TMS320C3x
SPRU194
TMS320C3x
circuit card assy input filter for miller 200 Dx
64 point radix 2 FFT
LM318 list
DSP101
74AS20 TTL
radix-4 DIT FFT C code
TLC32040C
TMS320
TMS320C31
TMS320C32
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GR-253
Abstract: STM-16 STS-48 XRT91L80 10P110 K 2666
Text: xr XRT91L80 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER JULY 2005 REV. P1.1.0 GENERAL DESCRIPTION control of the FIFO_AUTORST pin can automatically recover from an overflow condition. The operation of the device can be monitored by checking the status
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XRT91L80
STS-48/STM-16
XRT91L80
OC-48/STM-16
GR-253
STM-16
STS-48
10P110
K 2666
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VC5505
Abstract: 1C05h TMS320C5000 TMS320VC5505 XDS100 TMS320C55x TMS320C55 SPRUFP1 graphic display 8080 circuit diagram for wireless headsets
Text: TMS320VC5505 Fixed-Point Digital Signal Processor www.ti.com SPRS503 – JUNE 2009 1 Fixed-Point Digital Signal Processor • • • • • • • • • • High-Performance, Low-Power, TMS320C55x Fixed-Point Digital Signal Processor – 16.67-, 10-ns Instruction Cycle Time
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TMS320VC5505
SPRS503
TMS320C55xTM
10-ns
100-MHz
VC5505
1C05h
TMS320C5000
TMS320VC5505
XDS100
TMS320C55x
TMS320C55
SPRUFP1
graphic display 8080
circuit diagram for wireless headsets
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NO17
Abstract: NO11 TQ8032 TQ8032-M
Text: T R I Q U I N T S E M I C O N D U C T O R, I N C . TQ8032 64 32 x 32 Crosspoint Switch Matrix Input Buffers D0 – 31 CONFIGURE 800 Megabit/sec 32x32 Digital ECL Crosspoint Switch 64 Output Buffers O0 – 31 32 5-Bit Configuration Latches RESET IA0 – 4 OA0 – 4
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TQ8032
32x32
TQ8032
NO17
NO11
TQ8032-M
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jat52
Abstract: TA-TSY-000191 PM5319 PM5319-NI PMC-2030860
Text: us t, 20 04 09 :2 1: 24 PM ARROW 622 ASSP Telecom Standard Product Data Sheet Released es da y, 10 Au g PM5319 gi es , In c. on Tu ARROW 622 Released Issue No. 2: July 2004 Do wn lo ad ed by Sc o tt E st es of i 2T ec h no lo ASSP Telecom Standard Product Data Sheet
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PMC-2031158,
PM5319
196-pin
PM5319-NI
jat52
TA-TSY-000191
PM5319
PM5319-NI
PMC-2030860
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SPH-002T-P0.5S
Abstract: motorolla processor DSP56000 DSP56300 DSP56307 DSP56L307
Text: Order Number EB361/D: Rev. 1, 3/2001 MOTOROLA Semiconductor Products Sector Engineering Bulletin Functional Differences Between the Motorola DSP56307 and DSP56L307 The DSP56307 and DSP56L307, two members of the Motorola DSP56300 family of programmable digital signal processors
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EB361/D:
DSP56307
DSP56L307
DSP56L307,
DSP56300
DSP56000
EB361/D
SPH-002T-P0.5S
motorolla processor
DSP56L307
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cpcap motorola
Abstract: cpcap motorola cpcap motorola 8051 DSP56302 DSP56309 SC10 SC11 SC12 FF0000
Text: MOTOROLA Semiconductor Products Sector Engineering Bulletin Functional Differences Between DSP56302 and DSP56309 formerly DSP56302A 1 Purpose of this Document Order Number EB346/D: Rev. 2 4/20/2001 Contents 1 2 3 4 5 6 Purpose of this Document . 1
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DSP56302
DSP56309
DSP56302A)
EB346/D:
DSP302A;
DSP56309.
EB346/D
cpcap motorola
cpcap
motorola cpcap
motorola 8051
DSP56309
SC10
SC11
SC12
FF0000
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008 cow 734
Abstract: No abstract text available
Text: 80960CF-33, -25, -16 32-BIT HIGH PERFORMANCE SUPERSCALAR PROCESSOR • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 3'2-bit Burst Bus with Pipelining
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80960CF-33,
32-BIT
80960CA
64-bit
4fi2bl75
D141b21
008 cow 734
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Untitled
Abstract: No abstract text available
Text: in te i 0 M F [ i3 [m Y 0 N 80960CF-33, -25,-16 32-BIT HIGH PERFORMANCE SUPERSCALAR PROCESSOR • S o c k e t and O b jec t C o d e C o m p atib le w ith 8 0 96 0C A • T w o In s tru c tio n s /C lo c k S u stain ed E xecu tion • F ou r 59 M b y te s /s D M A C h an n els w ith D ata Chaining
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80960CF-33,
32-BIT
64-bit
2b175
4fl2bl75
01bbb4fl
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