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Teledyne e2v CY7C265-25WMB PROM, UV ERASABLE, 8K X 8, 25 NS - Rail/Tube (Alt: CY7C265-25WMB)
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Avnet Americas	CY7C265-25WMB	Tube			250	1 - 10 - 100 - 1000 - 10000 -	Get Quote
Teledyne e2v CY7C263-25WMB PROM, UV ERASABLE, 8K X 8, 25 NS ACCESS - Rail/Tube (Alt: CY7C263-25WMB)
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Avnet Americas	CY7C263-25WMB	Tube			250	1 - 10 - 100 - 1000 - 10000 -	Get Quote
Teledyne e2v QP7C245A-25WMB PROM, UV ERASABLE, 2K X 8, REGISTERED, 2 - Rail/Tube (Alt: QP7C245A-25WMB)
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Teledyne e2v QP7C263-25WMB PROM, UV ERASABLE, 8K X 8, 25 NS ACCESS - Rail/Tube (Alt: QP7C263-25WMB)
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Avnet Americas	QP7C263-25WMB	Tube			250	1 - 10 - 100 - 1000 - 10000 -	Get Quote
Teledyne e2v QP7C264-25WMB PROM, UV ERASABLE, 8K X 8, 25 NS ACCESS - Rail/Tube (Alt: QP7C264-25WMB)
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Avnet Americas	QP7C264-25WMB	Tube			250	1 - 10 - 100 - 1000 - 10000 -	Get Quote

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25WMB Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
C2665 Abstract: C2668 7c26 C2662 C266 27C64 CY7C266 R1250 C2666 Text: 1CY 7C26 6 CY7C266 8Kx8 Power-Switched and Reprogrammable PROM Features Functional Description • CMOS for optimum speed/power • Windowed for reprogrammability • High speed — 20 ns commercial — 25 ns (military) • Low power — 660 mW (commercial)	Original	CY7C266 CY7C266 600-mil-wide C2665 C2668 7c26 C2662 C266 27C64 R1250 C2666	PDF
74151 Abstract: 74151 pin connection C3406 74151 PIN DIAGRAM 74151 waveform counter schematic diagram 74161 programmer EPLD 22v10 5192JM 74151 multiplexer Text: 1CY 7C34 0 fax id: 6100 EPL D Family CY7C340 EPLD Family Multiple Array Matrix High-Density EPLDS Features tion of innovative architecture and state-of-the-art process, the MAX EPLDs offer LSI density without sacrificing speed. • Erasable, user-configurable CMOS EPLDs capable of	Original	CY7C340 CY7C34X) 65-micron CY7C34XB) 74151 74151 pin connection C3406 74151 PIN DIAGRAM 74151 waveform counter schematic diagram 74161 programmer EPLD 22v10 5192JM 74151 multiplexer	PDF
C3402 Abstract: 74151 5128LC-1 74151 PIN DIAGRAM 5128LC-2 74151 8 to 1 74151 pin connection function of 74151 22V10-10C CY7C340 Text: EPLD CY7C340 EPLD Family Multiple Array Matrix High-Density EPLDs Features • Erasable, user-configurable CMOS EPLDs capable of implementing high-density custom logic functions • 0.8-micron double-metal CMOS EPROM technology CY7C34X • Advanced 0.65-micron CMOS technology to increase	Original	CY7C340 CY7C34X) 65-micron CY7C34XB) C3402 74151 5128LC-1 74151 PIN DIAGRAM 5128LC-2 74151 8 to 1 74151 pin connection function of 74151 22V10-10C	PDF
transistor c331 Abstract: c331 transistor C3318 C3317 C331 C3311 C331 datasheet CY7C331 20HC c331 equivalent Text: CY7C331 Asynchronous Registered EPLD Features • Low power — 90 mA typical ICC quiescent • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — 180 mA ICC maximum — UV-erasable and reprogrammable — One feedback flip-flop with input coming from the	Original	CY7C331 CY7C331 transistor c331 c331 transistor C3318 C3317 C331 C3311 C331 datasheet 20HC c331 equivalent	PDF
27C64 Abstract: CY7C266 R1250 direct replacement Text: 66 CY7C266 8Kx8 Power-Switched and Reprogrammable PROM Features Functional Description • CMOS for optimum speed/power • Windowed for reprogrammability • High speed — 20 ns commercial — 25 ns (military) • Low power — 660 mW (commercial) The CY7C266 is a high-performance 8192 word by 8 bit	Original	CY7C266 CY7C266 600-mil-wide 27C64 R1250 direct replacement	PDF
74151 PIN DIAGRAM Abstract: 74151 22v10 5192JM CY7C340 PRODUCT CHANGE PALC22V10B programmer EPLD CY7C340 CY7C341B CY7C342B Text: 40 EPLD CY7C340 EPLD Family Multiple Array Matrix High-Density EPLDs Features • Erasable, user-configurable CMOS EPLDs capable of implementing high-density custom logic functions • 0.8-micron double-metal CMOS EPROM technology CY7C34X • Advanced 0.65-micron CMOS technology to increase	Original	CY7C340 CY7C34X) 65-micron CY7C34XB) 74151 PIN DIAGRAM 74151 22v10 5192JM CY7C340 PRODUCT CHANGE PALC22V10B programmer EPLD CY7C341B CY7C342B	PDF
C344 Abstract: 10HC 74HC 7C344 CY7C344 CY7C344B 7C344-25 TEA16 Text: fax id: 6101 1CY 7C34 4B CY7C344 CY7C344B 32-Macrocell MAX EPLD Features sents the densest EPLD of this size. Eight dedicated inputs and 16 bidirectional I/O pins communicate to one logic array block. In the CY7C344 LAB there are 32 macrocells and 64 expander product terms. When an I/O macrocell is used as an	Original	CY7C344 CY7C344B 32-Macrocell CY7C344 C344 10HC 74HC 7C344 CY7C344B 7C344-25 TEA16	PDF
C2653 Abstract: C2651 C2657 C2658 C2659 C2652 7c26 C2694 C2695 C265 Text: 1CY 7C26 5 CY7C265 8K x 8 Registered PROM Features If the asynchronous enable E is being used, the outputs may be disabled at any time by switching the enable to a logic HIGH, and may be returned to the active state by switching the enable to a logic LOW.	Original	CY7C265 7C265W) 28-pin, 300-mil C2653 C2651 C2657 C2658 C2659 C2652 7c26 C2694 C2695 C265	PDF
C2694 Abstract: C2695 C269-3 C2698 7C26 C269 CY7C269 C2697 cerdip z PACKAGE C2696 Text: 1CY 7C26 9 CY7C269 8K x 8 Registered Diagnostic PROM Features • EPROM technology — 100% programmable • CMOS for optimum speed/power • High speed commercial and military — 15-ns address set-up — Reprogrammable (7C269W) • 5V ±10% VCC, commercial and military	Original	CY7C269 15-ns 7C269W) 300-mil, 28-pin 12-ns CY7C269 C2694 C2695 C269-3 C2698 7C26 C269 C2697 cerdip z PACKAGE C2696	PDF
CY7C263-35PC Abstract: 7C261 CY7C263 CY7C26345DMB cerdip z PACKAGE 7C264 C261 CY7C261 CY7C264 f1b0 Text: CY7C261 CY7C263/CY7C264 CYPRESS Features • CMOS for optimum speed/power • Windowed for reprogrammability • High speed — 20 ns commercial — 25 ns (military) • Low power — 660 mW (commercial) — 770 m\V (military) • Super low standby power (7C261)	OCR Scan	CY7C261 C263/CY7C264 7C261) 300-mil 600-mil CY7C261, CY7C263, CY7C264 8192-word byGY7C264 CY7C263-35PC 7C261 CY7C263 CY7C26345DMB cerdip z PACKAGE 7C264 C261 f1b0	PDF
L496D Abstract: 9l reset CY7C331 ST L11922 0423-J Text: CY7C331 -W C Y P R E S S Asynchronous Registered EPLD Features • TWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coining from the I/O pin — Independent product term set,	OCR Scan	CY7C331 28-pin CY7C331 -40TMB 28-Lead CY7C331â 40WMB 28-Lead 300-Mil) L496D 9l reset ST L11922 0423-J	PDF
LC 7258 Abstract: 7C266 203CE Text: CY7C266 / CYPRESS 8K x 8 Power-Switched and Reprogrammable PROM Features • TTL-compatible I/O • CMOS for optimum speed/power • Direct replacement for 27C64 EPROMs • Windowed for reprogrammability • High speed — 20 ns commercial — 25 ns (military)	OCR Scan	CY7C266 CY7C266 32-Pin 28-Lead 600-Mil) LC 7258 7C266 203CE	PDF
74HC Abstract: 7C344 CY7C344 CY7C344B LTAC01 Text: CY7C344 CY7C344B i f CYPRESS 32-Macrocell MAX EPLD Features Functional Description • High-performance, high-density re placement for TTL, 74HC, and cus tom logic • 32 macrocells, 64 expander product terms in one LAB • 8 dedicated inputs, 16 I/O pins	OCR Scan	CY7C344 CY7C344B 32-Macrocell CY7C344) 65-micron CY7C344B) 28-pin 300-mil 74HC 7C344 LTAC01	PDF
Untitled Abstract: No abstract text available Text: CY7C332 ¡W CYPRESS SEMICONDUCTOR 13 in p u t m acrocells, each having: — C om plem entary input — R egister, latch, o r tra n s p a re n t access — Two clock sources Features • • Registered Combinatorial EPLD 12 I/O m acrocells each having: — R egistered, latched, o r tra n s p a re n t	OCR Scan	CY7C332 7C332	PDF

Untitled Abstract: No abstract text available Text: CY7C269 CYPRESS Features • CMOS for optimum speed/power • High speed commercial and military — 15-ns address set-up — 12-ns clock to output • Low power — 660 mW (commercial) — 770 mW (military) • On-chip edge-triggered registers — Ideal for pipelined micropro	OCR Scan	15-ns 12-ns 7C269W) 300-mil, 28-pin CY7C269 CY7C269	PDF
Untitled Abstract: No abstract text available Text: PRELIMINARY CYPRESS SEMICONDUCTOR Features 2K x 16 Reprogrammable State Machine PROM Functional Description The CY7C258 and CY7C259 are 2K x 16 CMOS PROMS specifically designed for — tcp = 12 ns use in state machine applications. — tcKO = 9 ns State machines are one of the most com	OCR Scan	CY7C258 CY7C259 16-bit-wide 83-MHz 0173-A CY7C258 CY7C259	PDF
Untitled Abstract: No abstract text available Text: CY7C344 CY7C344B y CYPRESS 32-Macrocell MAX EPLD Features Functional Description • High-performance, high-density re placement for TTL, 74HC, and cus tom logic • 32 macrocells, 64 expander product terms in one LAB • 8 dedicated inputs, 16 I/O pins	OCR Scan	CY7C344 CY7C344B 32-Macrocell CY7C344/CY7C344B	PDF
Untitled Abstract: No abstract text available Text: PLDC20G10B/PLDC20G10 CMOS Generic 24-Pin Reprogrammable Logic Device Generic architecture to replace stan dard logic functions including: 20L10, 20L8,20R8,20R6,20R4,12L10,14L8, 16L6,18L4,20L2, and 20V8 Eight product term s and one OE product term per output	OCR Scan	PLDC20G10B/PLDC20G10 24-Pin 20L10, 12L10 CG7C323 PLD20G10 28-pin 00019-F	PDF
74HC Abstract: 7C344 CY7C344 CY7C344B 20C02 DD131 Text: CY7C344 CY7C344B *0 CYPRESS 32-Macrocell MAX EPLD Features Functional Description • High-performance, high-density re placement for TTL, 74HC, and cus tom logic • 32 macrocells, 64 expander product terms in one LAB • 8 dedicated inputs, 16 I/O pins	OCR Scan	CY7C344 CY7C344B 32-Macrocell CY7C344) 65-micron CY7C344B) 28-pin 300-mil 74HC 7C344 20C02 DD131	PDF
RJH 30 a3 Abstract: No abstract text available Text: CY7C269 CYPRESS SEMICONDUCTOR • CMOS for optimum speed/power • High speed commercial and military — 15-ns max set-up — 12-ns clock to output • Low power — 660 mW (commercial) — 770 mW (military) • On-chip diagnostic shift register — For serial observability and con	OCR Scan	CY7C269 15-ns 12-ns 7C269W) 300-mil, 28-pin CY7C269 RJH 30 a3	PDF
Untitled Abstract: No abstract text available Text: CY7C291A CY7C292A/CY7C293A 'W CYPRESS = SEMICONDUCTOR Reprogrammable 2K x 8 PROM Features • Windowed for reprogrammability • CMOS for optimum speed/power • High speed — 2 0 ns commercial — 25 ns (military) • Low power — 660 mW (commercial and military)	OCR Scan	CY7C291A CY7C292A/CY7C293A 300-mil 600-mil CY7C291A, CY7C292A, CY7C293A CY7C292Aâ 35DMB CY7C293Aâ	PDF
CERAMIC LEADLESS CHIP CARRIER Abstract: la crosse technology smd UJ 99 7C245A CY7C245A 0G152 Text: W CYPRESS Features • • W indowed for reprogram m ability • C M O S for optim um speed/power • • • H igh speed — 15-ns ad dress set-up • — 10-ns clock to output • Low power — 330 m W com m ercial for —25 ns — 660 mW (m ilitary) •	OCR Scan	CY7C245A 15-ns 10-ns 300-mil, 24-pin CY7C245A progra8735 CY7C245Aâ 25LMB CERAMIC LEADLESS CHIP CARRIER la crosse technology smd UJ 99 7C245A 0G152	PDF
PALC22V10-30DMB Abstract: PALC22V10L-25WC PALC22V10-25DMB PALC22V10 p10j PALC22V10-35PC 22V10-25 cypress PALC22V10 22V10-30 PALC22V10L35PC Text: 4bE T> CYPRESS SEMICONDUCTOR 250=^5 OOQbTfciM 3 E K Y P PALC22V10 "“* cip R E S S SEMICONDUCTOR & 22 inputs and 10 outputs. When the win dowed cerDIP is exposed to UV light, the 22V10 is erased and can then be repro grammed. The programmable macrocell	OCR Scan	PALC22V10 PALC22V10L-35HC PALC22V10L-35JC PALC22V10L-35PC PALC22V10L-35WC PALC22V10-35HC PALC22V10 PALC22V10-35PC/PI PALC22V10-35WC/WI PALC22V10-40DMB PALC22V10-30DMB PALC22V10L-25WC PALC22V10-25DMB p10j PALC22V10-35PC 22V10-25 cypress PALC22V10 22V10-30 PALC22V10L35PC	PDF
333Q Abstract: CY7C269 C2692 Text: CY7C269 CYPRESS Features • • C M O S for optim um speed/pow er • H igh speed com m ercial and m ilitary — 15-ns ad dress set-up • — 12-ns clock to output • O n-chip d iagn ostic sh ift register — For serial ob servability and con trollab ility o f the ou tpu t register	OCR Scan	CY7C269 15-ns 12-ns 7C269W) 300-mil, 28-pin CY7C269 38-00069-G 001SS 333Q C2692	PDF

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Teledyne e2v CY7C265-25WMB

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Teledyne e2v QP7C245A-25WMB

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25WMB Datasheets Context Search

C2665

74151

C3402

transistor c331

27C64

74151 PIN DIAGRAM

C344

C2653

C2694

CY7C263-35PC

L496D

LC 7258

74HC

Untitled

Untitled

Untitled

Untitled

Untitled

74HC

RJH 30 a3

Untitled

CERAMIC LEADLESS CHIP CARRIER

PALC22V10-30DMB

333Q