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    Rochester Electronics LLC CY7C277-40WMB

    IC EPROM 256KBIT PARALLEL
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    DigiKey CY7C277-40WMB Bulk 1
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    Vishay Intertechnologies D55342K07B140WMBS

    D55342K 100PPM 1206 140 0.5% M BS - Bulk (Alt: D55342K07B140WMBS)
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    Avnet Americas D55342K07B140WMBS Bulk 19 Weeks 25
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    Teledyne e2v PALC16R8-40WMB

    PROG. LOGIC DEVICE, UV ERASABLE, 16-INPU - Rail/Tube (Alt: PALC16R8-40WMB)
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    Teledyne e2v PALC22V10-40WMB

    PROG. LOGIC DEVICE, UV ERASABLE, 22-INPU - Rail/Tube (Alt: PALC22V10-40WMB)
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    Teledyne e2v CY7C277-40WMB

    PROM, UV ERASABLE, 32K X 8, REGISTERED, - Rail/Tube (Alt: CY7C277-40WMB)
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    40WMB Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    transistor c331

    Abstract: c331 transistor C3318 C3317 C331 C3311 C331 datasheet CY7C331 20HC c331 equivalent
    Text: CY7C331 Asynchronous Registered EPLD Features • Low power — 90 mA typical ICC quiescent • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — 180 mA ICC maximum — UV-erasable and reprogrammable — One feedback flip-flop with input coming from the


    Original     		CY7C331 CY7C331 transistor c331 c331 transistor C3318 C3317 C331 C3311 C331 datasheet 20HC c331 equivalent PDF

    transistor c331

    Abstract: c331 transistor c331 c331 equivalent C3318 C3319 C3314 c3317 C3311 transistor c331 datasheet
    Text: fax id: 6016 1CY7C331 CY7C331 Asynchronous Registered EPLD Features • Low power — 90 mA typical ICC quiescent • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — 180 mA ICC maximum — UV-erasable and reprogrammable


    Original     		1CY7C331 CY7C331 transistor c331 c331 transistor c331 c331 equivalent C3318 C3319 C3314 c3317 C3311 transistor c331 datasheet PDF

    c331 equivalent

    Abstract: C3317 c331-12 c3311 192x pin diagram c331
    Text: CY7C331 Asynchronous Registered EPLD • Low power — 90 mA typical ICC quiescent Features • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — 180 mA ICC maximum — UV-erasable and reprogrammable — One feedback flip-flop with input coming from the I/O


    Original     		CY7C331 28-pin c331 equivalent C3317 c331-12 c3311 192x pin diagram c331 PDF

    L496D

    Abstract: 9l reset CY7C331 ST L11922 0423-J
    Text: CY7C331 -W C Y P R E S S Asynchronous Registered EPLD Features • TWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coining from the I/O pin — Independent product term set,


    OCR Scan     		CY7C331 28-pin CY7C331 -40TMB 28-Lead CY7C331â 40WMB 28-Lead 300-Mil) L496D 9l reset ST L11922 0423-J PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C330 C Y P R E S S •0 Features • Twelve I/O macrocells each having: — registered, three-state I/O pins — input register clock select multi­ plexer — feed back multiplexer — output enable OE multiplexer • All twelve macrocell state registers


    OCR Scan     		CY7C330 28-pin, 300-mil CY7C330â 28QMB 28-Pin 28TMB 28-Lead PDF

    Untitled

    Abstract: No abstract text available
    Text: Asynchronous Registered EPLD 13 inputs, 12 feedback VO pins, plus 6 shared I/O macrocell feedbacks for a total of 31 true and complementary inpnts High speed: 20 ns maximum tpo Security bit Space-saving 28-pin slim-line DIP package; also available in 28-pin


    OCR Scan     		28-pin 28-pin termW22 28-Lead 300-Mil) CY7C331 001305b PDF

    C3317

    Abstract: L1190 CY7331
    Text: Asynchronous Registered EPLD Features • TWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coming from the I/O pin — Independent product term set, reset, and clock inputs on all


    OCR Scan     		28-pin 28-Lead 28-Lead 300-Mil) CY7C331 0Dlb56b C3317 L1190 CY7331 PDF

    Untitled

    Abstract: No abstract text available
    Text: PLDC20G10B/PLDC20G10 CMOS Generic 24-Pin Reprogrammable Logic Device Generic architecture to replace stan­ dard logic functions including: 20L10, 20L8,20R8,20R6,20R4,12L10,14L8, 16L6,18L4,20L2, and 20V8 Eight product term s and one OE product term per output


    OCR Scan     		PLDC20G10B/PLDC20G10 24-Pin 20L10, 12L10 CG7C323 PLD20G10 28-pin 00019-F PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C335 / CYPRESS Features • 100-MHz output registered operation • Twelve I/O macrocells, each having: — Registered, three-state I/O pins — Input and output register clock se­ lect m ultiplexer — Feed back multiplexer — Output enable OE multiplexer


    OCR Scan     		CY7C335 100-MHz 300-M 28-Square 7C335â 38-00186-C PDF

    20G10B-20

    Abstract: 12L10 16L6 18L4 20L10 20L8
    Text: r PLDC20G10B/PLDC20G10 CYPRESS Features • Fast — Commercial: tpn = 15 ns, tc o = ID us, tg = 12 ns — Military: tPD = 20 ns, tc o = 15 ns, ts — 15 ns • Low power — Ice max.: 70 mA, commercial — Ic e max.: 100 mA, military • Commercial and m ilitary tem perature


    OCR Scan     		PLDC20G10B/PLDC20G10 24-Pin 20L10, 12L10, 24-Lead 300-Mil) PLDC20G10â CG7C323 20G10B-20 12L10 16L6 18L4 20L10 20L8 PDF

    aj4 diode

    Abstract: CY7C277 658f 7C277
    Text: CYPRESS 4bE SEMICONDUCTOR J /s S - I SSfl'lbbS GG0bôb3 fl B C Y P D CY7C277 CY7C279 CYPRESS SEMICONDUCTOR Reprogrammable 32K x 8 Registered PROM Programmable address latch enable input Programmable synchronous or asynchronous output enable 7C277 On-chip edge-triggered output


    OCR Scan     		00Dbflb3 CY7C277 CY7C279 7C277) 7C279) aj4 diode 658f 7C277 PDF

    2SUR

    Abstract: CY7C331 L1190 C3317
    Text: CY7C331 ¿F C Y P R E S S Features • TWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coining from the I/O pin — Independent product term set, reset, and clock inpnts on all


    OCR Scan     		CY7C331 28-pin 40HMB CY7C331â 40LMB 28-Square 40QMB 2SUR L1190 C3317 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C277 CY7C279 CYPRESS SEMICONDUCTOR Features Reprogrammable 32K x 8 Registered PROM Programmable address latch enable input Programmable synchronous or asynchronous output enable 7C277 On-chip edge-triggered output registers (7C277) Optional registered/latched address


    OCR Scan     		CY7C277 CY7C279 7C277) 7C279) 300-mil, 28-pin PDF

    Untitled

    Abstract: No abstract text available
    Text: s rs y CYPRESS SEMICONDUCTOR Features • TWelve I/O macrocells each having: — registered, three-state I/O pins — input register clock select multi­ plexer — feed back multiplexer — output enable OE multiplexer • All twelve macrocell state registers


    OCR Scan     		CY7C330 28-pin, 300-mil CY7C330â 28DMB 28HMB 28LMB PDF

    65842

    Abstract: 333Q CERAMIC LEADLESS CHIP CARRIER ci 4030 CY7C277
    Text: CY7C277 CYPRESS Features • Windowed for reprogrammability • CMOS for optimum speed/power • High speed — 30-ns address set-up — 15-ns clock to output • Low power — 660 mW commercial — 715 raW (military) • Programmable address latch enable


    OCR Scan     		30-ns 15-ns 300-mil, 28-pin 15-BIT X1024 CY7C277â 50QMB 32-Pin 65842 333Q CERAMIC LEADLESS CHIP CARRIER ci 4030 CY7C277 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C277 CYPRESS SEMICONDUCTOR Reprogrammable 32K x 8 Registered PROM • Programmable address latch enable input • Programmable synchronous or asynchronous output enable • On-chip edge-triggered output registers • EPROM technology, 100% programmable


    OCR Scan     		CY7C277 300-mil, 28-pin 30-ns 15-ns CY7C277â 40QMB 28-Lead 300-Mil) PDF

    PALC22V10

    Abstract: 22V10-35 PALC22V10-25dmb PALC22V10-40DMB PALC22V10L35PC PALC22V10 20HC PALC22V10L-25JC PALC22V10-35PC
    Text: PALC22V10 CYPRESS SEMICONDUCTOR • Up to 22 input terms and 10 outputs • High reliability — Proven EPROM technology — 100% programming and functional testing Features • Advanced second-generation PAL architecture • Low power — 55 mA max. “IT


    OCR Scan     		PALC22V10 22V10 LC22V10L-35HC PALC22V10L-35JC PALC22V10L-35PC PALC22V10L-- PALC22V10-- 35JC/J1 PALC22V10-35PC/PI PALC22V10 22V10-35 PALC22V10-25dmb PALC22V10-40DMB PALC22V10L35PC PALC22V10 20HC PALC22V10L-25JC PALC22V10-35PC PDF

    7C332

    Abstract: No abstract text available
    Text: CY7C335 Universal Synchronous EPLD V CYPRESS Features • 100-MHz output registered operation • Twelve I/O macrocells, each having: — Registered, three-state I/O pins — Input and output register clock se­ lect multiplexer — Feed back multiplexer — Output enable OE multiplexer


    OCR Scan     		100-MHz CY7C335 cl300-Mil) 28-Pin 28-Lead 300-Mil) 7C332 PDF