Untitled
Abstract: No abstract text available
Text: MITSUBISHI LSIs DRAM MODULE FAST PAGE MODE DYNAMIC RAM 4M x 32 1 I f a O M BIT 2 8 Max. Access Type name Load memory time Outward dimensions Data sheet W X H X D (mm) page 59.69 X 25.4 x 3.8 3 /1 5 (ns) MH4M32AJJ-6 * 60 MH4M32ANJJ-6 MH4M32AJJ-7 ★★ M5M417400ATP, RT
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MH4M32AJJ-6
MH4M32ANJJ-6
MH4M32AJJ-7
MH4M32ANJJ-7
M5M417400ATP,
134217728-BIT
4194304-WORD
32-BIT
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TMP95C061F
Abstract: TMP95C0618 ti67 TMP95C061 FUNCTIONING OF A WATCH MOTOR tmp96c061 TLCS-900 IC 74hcxx 0FFFF02H
Text: TOSHIBA TLCS-900 Series CMOS 16-bit Microcontrollers TMP95C061F 1. Outline and Device Characteristics TMP95C061F is a high-speed advanced 16-bit microcontroller developed for controlling medium to large-scale equipment. The TMP95C061F is housed in an 100-pin flat package.
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TLCS-900
16-bit
TMP95C061F
TMP95C061F
100-pin
TLCS-90/900
16M-byte
TMP95C0618
ti67
TMP95C061
FUNCTIONING OF A WATCH MOTOR
tmp96c061
IC 74hcxx
0FFFF02H
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RF93
Abstract: RF72 RF89 rf74 RF76 rf66 RF86 RF92 DRAM Controller RF68
Text: A AP-712 APPLICATION NOTE DRAM Controller for i960 JA/JF/JD Microprocessors Paul Durazo SPG EPD 80960 Applications Engineer Intel Corporation Embedded Processor Division Mail Stop CH5-233 5000 W. Chandler Blvd. Chandler, Arizona 85226 February 9, 1995 Order Number: 272674-001
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AP-712
CH5-233
74F257)
RF93
RF72
RF89
rf74
RF76
rf66
RF86
RF92
DRAM Controller
RF68
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AM-204M
Abstract: AM21 SM5906AF
Text: SM5906AF Shock-proof Memory Controller for Video CD Players NIPPON PRECISION CIRCUITS INC. Overview The SM5906AF is a shock-proof memory controller LSI for video CD players. The operating mode can be set to CD-DA mode, V-CD mode, or Super V-CD mode, and external memory can be selected from 2
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SM5906AF
SM5906AF
16-bit/MSB
16/24/32-bit
384fs
NC9901AE
CIRCUITS-30
AM-204M
AM21
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82c597
Abstract: 83C206 Cyrix 486 dx2 CX486 386DX CY82C597 intel 486 dx4 t324 amd 386 PC MOTHERBOARD diagram cyrix DX2
Text: PRELIMINARY CY82C597 386/486 Green Chip Set D Features Page mode DRAM controller supports mixture of 256KB/512KB/1MB/2MB/ 4MB/16MB devices D D MicrosoftR APM support 11 event detectors and 5 userĆdefined timers D D 160ĆPin single chip PQFP Supports PC/AT compatible systems
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CY82C597
256KB/512KB/1MB/2MB/
4MB/16MB
160Pin
128MB
32KB/64KB/128KB/256KB/512KB/
82c597
83C206
Cyrix 486 dx2
CX486
386DX
CY82C597
intel 486 dx4
t324
amd 386 PC MOTHERBOARD diagram
cyrix DX2
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DSP56301
Abstract: No abstract text available
Text: AC Electrical Characteristics Port A Port A VCC = 3.3 V ± 0.3 V; TJ = −40˚C to +100 ˚C, CL = 50 pF + 2 TTL Loads Table 8 SRAM Read and Write Accesses No. 100 101 102 103 Characteristics Address Valid and AA Assertion Pulse Width Address Valid to WR Assertion
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DSP56301
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Untitled
Abstract: No abstract text available
Text: TO SH IB A TMP94C251 CMOS 32-bit Micro-controller TMP94C251F 1. OUTLINE AND DEVICE CHARACTERISTICS TMP94C251 is high-speed advanced 32-bit micro-controller developed for controlling equipm ent which processes mass data. TMP94C251 is a micro-controller which has a high-performance CPU 900/H2 CPU and various
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TMP94C251
32-bit
TMP94C251F
TMP94C251
900/H2
144-pin
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AM20
Abstract: CMP12 SM5901AF CAS-000 MN662
Text: SM5901AF compression and non compression type anti-shock memory controller with built-in 1M DRAM NIPPON PRECISION CIRCUITS INC. Overview 1M DRAM can be connected to expand the memory to 2M bits. Digital attenuator, soft mute and related functions are also incorporated. It operates from
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SM5901AF
384fs
NC9607BE
AM20
CMP12
SM5901AF
CAS-000
MN662
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TMP94C241AF
Abstract: 10T50- timer tmp94c241a 8T100 M1S21 TLCS-900 rele 5v B4CS TMP94CS40 p41c
Text: TO SHIBA TMP94C241A CMOS 32-bit Micro-controller TMP94C241AF 1. OUTLINE AND DEVICE CHARACTERISTICS TMP94C241A is high-speed advanced 32-bit micro-controller developed for controlling equipment which processes mass data. TMP94C241A is a micro-controller which has a high-performance CPU 900/H2 CPU and various
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TMP94C241A
32-bit
TMP94C241AF
TMP94C241A
900/H2
160-pin
TMP94C241AF
10T50- timer
8T100
M1S21
TLCS-900
rele 5v
B4CS
TMP94CS40
p41c
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PHCR 359
Abstract: 10T50- timer operation manual
Text: TOSHIBA UNDER DEVELOPMENT TMP94C241F CMOS 32-bit Micro-controller TMP94C241F 1. OUTLINE AND DEVICE CHARACTERISTICS TMP94C241F is high-speed advanced 32-bit micro-controller developed for controlling equipment which processes mass data. TMP94C241F is a micro-controller which has a high-performance CPU 900/H2 CPU
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TMP94C241F
32-bit
TMP94C241F
900/H2
160-pin
PHCR 359
10T50- timer operation manual
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tda1316
Abstract: tda1316 write amplifier CHN 712 tda1316 write SAA7323 SAA2022 TDA1317 Q445 SAA2022GP SAA2032
Text: Product specification Philips Sem iconductors Tape formatting and error correction for the DCC system S A A 2022 FEATURES • Integrated error correction encoder/decoder function with Digital Compact Cassette DCC optimized algorithms COMPACT CASSETTE • Control of capstan servo during recording and after
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CLK24.
CLK24
tda1316
tda1316 write amplifier
CHN 712
tda1316 write
SAA7323
SAA2022
TDA1317
Q445
SAA2022GP
SAA2032
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CMP12
Abstract: SM5903BF 18 pins telephon ics cxd2517
Text: SM5903BF compression and non compression type shock-proof memory controller NIPPON PRECISION CIRCUITS INC. Overview The SM5903BF is a compression and non compression type shock-proof memory controller LSI for compact disc players. The compression level can
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SM5903BF
SM5903BF
16-bit/MSB
15-bit
16-bit
NC9819AE
CIRCUITS-31
CMP12
18 pins telephon ics
cxd2517
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STP2013
Abstract: Mbus master 250 slave circuit STP2013PGA-50 m-bus mbus STP2011 STP2013PGA50 MAD44
Text: STP2013PGA-50 July 1997 EMC DATA SHEET Error-Correcting Memory Controller DESCRIPTION The STP2013 Error-Correcting Memory Controller control mechanism consists of a central arbiter that selects between MBus and graphics-request masters, while monitoring periodic refresh and VIO preemptive interrupts. Satellite state machines are granted execution by the arbiter in response to a buffered request. Stalled
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STP2013PGA-50
STP2013
STP2013PGA
299-Pin
STP2013
Mbus master 250 slave circuit
STP2013PGA-50
m-bus
mbus
STP2011
STP2013PGA50
MAD44
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CMP12
Abstract: SM5901AF
Text: DISCONTINUED PRODUCT SM5901AF compression and non compression type anti-shock memory controller with built-in 1M DRAM NIPPON PRECISION CIRCUITS INC. Overview Features •Digital attenuator im ina - 2-channel processing 1M DRAM can be connected to expand the memory to 2M bits. Digital attenuator, soft mute and related functions are also incorporated. It operates from
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SM5901AF
SM5901
16-bit/MSB
384fs
16roducts
NC9607BE
CIRCUITS-31
CMP12
SM5901AF
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M1S21
Abstract: PDCR 900 TLCS-900 TMP94C251A TMP94C251AF m1s23 IRS rele
Text: TO SH IB A TMP94C251A CMOS 32-bit M icro con tro ller TMP94C251AF 1. Outline and Device Characteristics TMP94C251A is high-speed advanced 32-bit micro-controller developed for controlling equipm ent which processes m ass data. TMP94C251A is a micro-controller which has a high-performance CPU 900/H2 CPU and various
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TMP94C251A
32-bit
TMP94C251AF
TMP94C251A
900/H2
144-pin
M1S21
PDCR 900
TLCS-900
TMP94C251AF
m1s23
IRS rele
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microcont
Abstract: CMP12 SM5859AF
Text: SM5859AF compression and non compression type antishock memory controller NIPPON PRECISION CIRCUITS INC. Overview The SM5859 is a compression and non compression type anti-shock memory controller LSI for compact disc players. The compression level can be set
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SM5859AF
SM5859
16-bit/MSB
384fs
NC9605DE
CIRCUITS-33
microcont
CMP12
SM5859AF
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CMP12
Abstract: SM5904CF CXD2517
Text: SM5904CF compression and non compression type shock-proof memory controller NIPPON PRECISION CIRCUITS INC. Overview The SM5904CF is a compression and non compression type shock-proof memory controller LSI for compact disc players. The compression level can
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SM5904CF
SM5904CF
16-bit/MSB
NC9926AE
CIRCUITS-35
CMP12
CXD2517
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CMP12
Abstract: SM5905AF
Text: SM5905AF compression and non compression type shock-proof memory controller NIPPON PRECISION CIRCUITS INC. Overview The SM5905AF is a compression and non compression type shock-proof memory controller LSI for compact disc players. The compression level can
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SM5905AF
SM5905AF
16-bit/MSB
384fs
NC9814BE
CIRCUITS-35
CMP12
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PDF
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PQFP128
Abstract: HYB39M83200 HYB39M83200L HYB39M83200Q HYB39M93200 HYB39M93200L HYB39M93200Q PLCC68 PQFP-128 TQFP-100
Text: 288k x 32 / 256k x 32 M ULTIBANK DRAM M DRAM HYB39M93200 HYB39M83200 Preliminary Information * Ultra-High Performance 666 M B yte/sec single device transfer rate 36 ns RAS access 13.8 ns CAS access 6 ns burst cycle * Multibank Architecture RAS and precharge may overlap CAS READ or W R ITE to different banks effectively hiding
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HYB39M93200
HYB39M83200
HYB39M93200Q
288kx
PQFP128
HYB39M93200L
PLCC68
HYB39M83200Q
256kx
PQFP128
HYB39M83200
HYB39M83200L
PLCC68
PQFP-128
TQFP-100
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tlcs-900
Abstract: TMP96C031F TLCS-90 TMP96C031N IC 74hcxx
Text: TOSHIBA TLCS-900 Series CMOS 16-bit Microcontrollers TMP96C031N/TMP96C031F 1. Outline and Device Characteristics The TMP96C031 are high-speed advanced 16-bit microcontrollers developed for controlling medium to large-scale equipment. TMP96C031N comes in a 64-pin shrink DIP; the
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TLCS-900
16-bit
TMP96C031N/TMP96C031F
TMP96C031
TMP96C031N
64-pin
TMP96C031F,
TMP96C031F
TLCS-90
IC 74hcxx
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DSP56300
Abstract: DSP56303 G38-87 AA0482
Text: SECTION 2 SPECIFICATIONS INTRODUCTION The DSP56303 is fabricated in high density CMOS with Transistor-Transistor Logic TTL compatible inputs and outputs. The DSP56303 specifications are preliminary and are from design simulations, and may not be fully tested or
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DSP56303
AA0500
DSP56303/D
DSP56300
G38-87
AA0482
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TAZ BI-DIR
Abstract: Mbus master 250 slave circuit STP2103 MAD32
Text: S un M ic r o e le c t r o n ic s July 1997 EMC DATA SHEET Error-Correcting Memory Controller D e s c r ip t io n The STP2013 Error-Correcting Memory Controller control mechanism consists of a central arbiter that selects between MBus and graphics-request masters, while monitoring periodic refresh and VIO preemptive inter
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STP2013
STP2013
TAZ BI-DIR
Mbus master 250 slave circuit
STP2103
MAD32
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Response AA0482
Abstract: AA0463 AA0470 AA0482 284 278 DSP56300 DSP56302 G38-87 AA-0481 AA0460
Text: SECTION 2 SPECIFICATIONS INTRODUCTION The DSP56302 is fabricated in high density CMOS with Transistor-Transistor Logic TTL compatible inputs and outputs. The DSP56302 specifications are preliminary and are from design simulations, and may not be fully tested or
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DSP56302
AA0500
DSP56302/D
Response AA0482
AA0463
AA0470
AA0482
284 278
DSP56300
G38-87
AA-0481
AA0460
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CMP12
Abstract: SM5904BF CAS-000
Text: SM5904BF compression and non compression type shock-proof memory controller NIPPON PRECISION CIRCUITS INC. Overview The SM5904BF is a compression and non compression type shock-proof memory controller LSI for compact disc players. The compression level can
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Original
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SM5904BF
SM5904BF
16-bit/MSB
NC9820BE
CIRCUITS-35
CMP12
CAS-000
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