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    32BITS Search Results

    32BITS Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TMPM3HMFYAFG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP80-1212-0.50-003 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM3HPFYADFG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP128-1420-0.50-001 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM3HLFYAUG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP64-1010-0.50-003 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM3HNFZAFG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP100-1414-0.50-002 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM3HLFZAUG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP64-1010-0.50-003 Visit Toshiba Electronic Devices & Storage Corporation

    32BITS Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    45VM32160D

    Abstract: No abstract text available
    Text: IS42/45VM32160D 4M x 32Bits x 4Banks Mobile Synchronous DRAM Description These IS42/45VM32160D are mobile 536,870,912 bits CMOS Synchronous DRAM organized as 4 banks of 4,194,304 words x 32 bits. These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs are


    Original     		PDF IS42/45VM32160D 32Bits IS42/45VM32160D -40oC 16Mx32 IS42VM32160D-6BLI IS42VM32160D-75BLI 90-ball 45VM32160D

    ba1s

    Abstract: No abstract text available
    Text: IS43LR32400E Advanced Information 1M x 32Bits x 4Banks Mobile DDR SDRAM Description The IS43LR32400E is 134,217,728 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 1,048,576 words x 32 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The address lines are multiplexed with the Data


    Original     		PDF IS43LR32400E 32Bits IS43LR32400E Figure38 90Ball -25oC 4Mx32 IS43LR32400E-6BLE ba1s

    SM32200K

    Abstract: IS42SM32200K
    Text: IS42SM/RM/VM32200K 512K x 32Bits x 4Banks Mobile Synchronous DRAM Description These IS42SM/RM/VM32200K are mobile 67,108,864 bits CMOS Synchronous DRAM organized as 4 banks of 524,288 words x 32 bits. These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs are


    Original     		PDF IS42SM/RM/VM32200K 32Bits IS42SM/RM/VM32200K 200K-6BLI IS42SM32200K-75BLI 90-ball -40oC 2Mx32 IS42RM32200K-6BLI SM32200K IS42SM32200K

    46LR32640A

    Abstract: Mobile DDR SDRAM
    Text: IS43/46LR32640A 16M x 32Bits x 4Banks Mobile DDR SDRAM Description The IS43/46LR32640A is 2,147,483,648 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 33,554,432 words x 32 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted


    Original     		PDF IS43/46LR32640A 32Bits IS43/46LR32640A 32-bit IS43LR32640A-6BLI 90-ball -40oC 64Mx32 IS46LR32640A-5BLA1 46LR32640A Mobile DDR SDRAM

    Untitled

    Abstract: No abstract text available
    Text: N32D3225LPAW 512K x 32Bits x 2Banks Low Power Synchronous DRAM Description These N32D3225LPAW are low power 33,554,432 bits CMOS Synchronous DRAM organized as 2 banks of 524,288 words x 32 bits. These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs are


    Original     		PDF N32D3225LPAW 32Bits N32D3225LPAW

    Untitled

    Abstract: No abstract text available
    Text: N128D3218LPAF2 Advance Information 1M x 32Bits x 4Banks Mobile Synchronous DRAM Description These N128D3218LPAF2 are mobile 134,217,728 bits CMOS Synchronous DRAM organized as 4 banks of 1,048,576 words x 32 bits. These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs are


    Original     		PDF N128D3218LPAF2 32Bits N128D3218LPAF2

    Untitled

    Abstract: No abstract text available
    Text: IS42RM32400F Advanced Information 1M x 32Bits x 4Banks Mobile Synchronous DRAM Description These IS42RM32400F are mobile 134,217,728 bits CMOS Synchronous DRAM organized as 4 banks of 1,048,576 words x 32 bits. These products are offering fully synchronous operation and are


    Original     		PDF IS42RM32400F 32Bits IS42RM32400F 90Ball -25oC 4Mx32 IS42RM32400F-6BLE IS42RM32400F-75BLE

    Untitled

    Abstract: No abstract text available
    Text: HY5W2A2 L/S F / HY57W2A3220(L/S)T HY5W22F / HY57W283220T 4Banks x 1M x 32bits Synchronous DRAM Revision History Revision No. History 0.3 Changed TA, PKG Drawing, Output Load Circuit 0.4 Changed Cin Value. 0.6 1. Added Operation Code in Mode Register 2. Changed Burst Stop in Full Page


    Original     		PDF HY57W2A3220 HY5W22F HY57W283220T 32bits HY5W22CF

    Untitled

    Abstract: No abstract text available
    Text: W9864G2JH 512K  4 BANKS  32BITS SDRAM Table of Contents1. GENERAL DESCRIPTION . 3 2. FEATURES . 3


    Original     		PDF W9864G2JH 32BITS

    W9864G2GH-6I

    Abstract: W9864G2GH W9864G2GH-5
    Text: W9864G2GH 512K X 4 BANKS X 32BITS SDRAM Table of Contents1. GENERAL DESCRIPTION . 3 2. FEATURES . 3


    Original     		PDF W9864G2GH 32BITS W9864G2GH-6I W9864G2GH W9864G2GH-5

    ESA2UN3282B-60JS-S

    Abstract: EDO RAM drawing
    Text: July 1997 Revision 1.0 data sheet ESA2UN3282B-60JS-S 8MByte 2M x 32 CMOS EDO DRAM Module General Description The ESA2UN3282B-60JS-S is a high performance, EDO (Extended Data Out) 8-megabyte dynamic RAM module organized as 2M words by 32bits, in a 72-pin, leadless, single-in-line memory module (SIMM) package. ESA2UN3282B supports 2K refresh.


    Original     		PDF ESA2UN3282B-60JS-S ESA2UN3282B-60JS-S 32bits, 72-pin, ESA2UN3282B MB8117805B-60PJ MP-DRAMM-DS-20546-7/97 EDO RAM drawing

    20549

    Abstract: No abstract text available
    Text: July 1997 Revision 1.0 data sheet ESA4UN3242B- 50/60 (J/T)(G/S)-S 16MByte (4M x 32) CMOS EDO DRAM Module General Description The ESA4UN3242B-(50/60)(J/T)(G/S)-S is a high performance, EDO (Extended Data Out)16-megabyte dynamic RAM module organized as 4M words by 32bits, in a 72-pin, leadless, single-in-line memory module (SIMM) package. ESA4UN3242B supports


    Original     		PDF ESA4UN3242B- 16MByte 16-megabyte 32bits, 72-pin, ESA4UN3242B MB8117405B- MP-DRAMM-DS-20549-7/97 20549

    JSs 57

    Abstract: No abstract text available
    Text: February 1997 Revision 1.0 data sheet ESA2UN3282 A -(60/70)JS-S 8MByte (2M x 32) CMOS EDO DRAM Module General Description The ESA2UN3282(A)-(60/70)JS-S is a high performance, EDO (Extended Data Out) 8-megabyte dynamic RAM module organized as 2M words by 32bits, in a 72-pin, leadless, single-in-line memory module (SIMM) package. ESA2UN3282(A) supports 2K refresh.


    Original     		PDF ESA2UN3282 32bits, 72-pin, MB8117805A- JSs 57

    1Mx4 dram simm

    Abstract: 1Mx4 EDO RAM ESA2UN3241A-60JS-S
    Text: July 1997 Revision 1.0 data sheet ESA2UN3241A- 60/70 JS-S 8MByte (2M x 32) CMOS EDO DRAM Module General Description The ESA2UN3241A-(60/70)JS-S is a high performance, EDO (Extended Data Out) 8-megabyte dynamic RAM module organized as 2M words by 32bits, in a 72-pin, leadless, single-in-line memory module (SIMM) package.


    Original     		PDF ESA2UN3241A- 32bits, 72-pin, MB814405D- 60/70ns) MP-DRAMM-DS-20548-7/97 1Mx4 dram simm 1Mx4 EDO RAM ESA2UN3241A-60JS-S

    46LR32640A

    Abstract: Mobile DDR SDRAM IS43LR32640A-5BLI IS46LR32640A-5BLA1 64Mx32 Mobile DDR SDRAM IS43LR32640A
    Text: IS43/46LR32640A Advanced Information 16M x 32Bits x 4Banks Mobile DDR SDRAM Description The IS43/46LR32640A is 2,147,483,648 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 33,554,432 words x 32 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted


    Original     		PDF IS43/46LR32640A 32Bits IS43/46LR32640A 32-bit IS43LR32640A-5BL IS43LR32640A-6BL 90-ball -40oC 64Mx32 46LR32640A Mobile DDR SDRAM IS43LR32640A-5BLI IS46LR32640A-5BLA1 64Mx32 Mobile DDR SDRAM IS43LR32640A

    SM32800E

    Abstract: IS42RM32800E
    Text: IS42/45SM/RM/VM32800E 2M x 32Bits x 4Banks Mobile Synchronous DRAM Description These IS42/45SM/RM/VM32800E are mobile 268,435,456 bits CMOS Synchronous DRAM organized as 4 banks of 2,097,152 words x 32 bits. These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs


    Original     		PDF IS42/45SM/RM/VM32800E 32Bits IS42/45SM/RM/VM32800E IS42SM32800E-75BLI 90-ball -40oC 8Mx32 IS42RM32800E-6BLI IS42RM32800E-75BLI SM32800E IS42RM32800E

    Untitled

    Abstract: No abstract text available
    Text: N128D3233LPAF2 Advance Information 1M x 32Bits x 4Banks Mobile Synchronous DRAM Description These N128D3233LPAF2 are mobile 134,217,728 bits CMOS Synchronous DRAM organized as 4 banks of 1,048,576 words x 32 bits. These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs are


    Original     		PDF N128D3233LPAF2 32Bits N128D3233LPAF2

    Untitled

    Abstract: No abstract text available
    Text: N32D3225LPAF2 512K x 32Bits x 2Banks Low Power Synchronous DRAM Description These N32D3225LPAF2 are low power 33,554,432 bits CMOS Synchronous DRAM organized as 2 banks of 524,288 words x 32 bits. These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs are


    Original     		PDF N32D3225LPAF2 32Bits N32D3225LPAF2

    QUANTA power sequence

    Abstract: VIA VT6212L VT6212 quanta VT6212L P0V75 rt8101l quanta computer foxconn CMM211T-900M-S
    Text: 1 2 PCIe-1 SM BUS A 3 4 5 6 CPPE# POWER IC CPUSB# RICOH/ R5535V PCI-e 1 SM BUS PCI-e 2 PAD , HOLE NEW CARD CONN. PG 20 A PG 11 USB HOST INTEL 8 3V/ 1.5V USB 0 PCIe-2 7 VIA VT6212L-1 PCI BUS/ 33MHz/ 32bits USB 2 INTA,B,C REQ0 GNT0 AD18 PG 12 PCI-e to PCI Bridge


    Original     		PDF R5535V VT6212L-1 33MHz/ 32bits VT6212L-2 IEEE1394 43AB22A REQX181 PAD19 QUANTA power sequence VIA VT6212L VT6212 quanta VT6212L P0V75 rt8101l quanta computer foxconn CMM211T-900M-S

    DTMF mobile

    Abstract: V30HL CISC OP BASEBAND 80MHZ Reed-Solomon CODEC G711 M80186 V20HL dsp oak pine CIS scanner
    Text: Intellectual Property ROHM Intellectual Property CPU -32bits R IS -16bits(C C ARM7TDMI *1 IS -16bits(C C)V30HL/V20HL *2 IS -8bits(CIS C)M80186 C -4bits(CIS )M8052 C) DRAM(e -Embeded RAM) *3 DRAM -Dual Po rt -FIFO Non-vola -ISDN Analog tile mem -FLASH -EEPRO


    Original     		PDF -32bits -16bits V30HL/V20HL M80186 M8052 -M320C5 -M320C2 -10bit 10Msps DTMF mobile V30HL CISC OP BASEBAND 80MHZ Reed-Solomon CODEC G711 M80186 V20HL dsp oak pine CIS scanner

    HY57V643220D

    Abstract: hy57v643220dt HY57V643220
    Text: Preliminary HY57V643220D L/S T(P) Series 4Banks x 512K x 32bits Synchronous DRAM Document Title 4Bank x 512K x 32bits Synchronous DRAM Revision History Revision No. History Draft Date Remark 0.1 Initial Draft May. 2004 Preliminary This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for


    Original     		PDF HY57V643220D 32bits 864bit A10/AP hy57v643220dt HY57V643220

    HY57V643220D

    Abstract: No abstract text available
    Text: Preliminary HY57V643220D L/S T(P)-xI Series 4Banks x 512K x 32bits Synchronous DRAM Document Title 4Bank x 512K x 32bits Synchronous DRAM Revision History Revision No. History Draft Date Remark 0.1 Initial Draft June. 2004 Preliminary This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for


    Original     		PDF HY57V643220D 32bits 864bit A10/AP

    Untitled

    Abstract: No abstract text available
    Text: 256Mb Synchronous DRAM based on 2M x 4Bank x32 I/O Document Title 4Bank x 2M x 32bits 4Bank x2M x16 *2 Stack Synchronous DRAM Revision History Revision No. History Draft Date Remark 0.1 Initial Draft Jul. 2005 Preliminary This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for


    Original     		PDF 256Mb 32bits 11Preliminary 256Mbit 8Mx16bit HY5V52E 456bit

    n343532

    Abstract: N343532LQF-8N n343532lqf8 DS-N343532-12 N343532LTQ8 N343532LTQ-8 N343532LTQ-10 N343532LQF n343532lqf8n N343532LQF-8
    Text: CMOS NKK Low Voltage SRAM Fast Synchronous with Burst Counter 1M-BIT 32K X 32 N343532L -K. -N • Features • CMOS SRAM organized as 32,768 X 32bits • Single+3.3V Power Supply • Fast Clock Access time : 8ns/66MHz, l0ns/60M Hz, 12ns/50MHz • Synchronous operation


    OCR Scan     		PDF N343532L 32bits 8ns/66MHz, l0ns/60M 12ns/50MHz N343532LQF-8 N343532LTQ-8 N343532LQF-10 N343532LTQ-10 N343532LQF-12 n343532 N343532LQF-8N n343532lqf8 DS-N343532-12 N343532LTQ8 N343532LQF n343532lqf8n