350MIL Search Results

4A04I

Abstract: tc514100a
Contextual Info: TC51441OAP/AJ/ASJ/AZ—70, TC51441OAP/AJ/ASJ/AZ-80 TC51441OAP/AJ/ASJ/AZ-10 PRELIMINARY 1,048,576 W ORD x 4 BIT DYNAMIC RAM DESCRIPTION The TC51441 OAP/AJ/ASJ/AZ is the new generation dynamic RAM organized 1,048,576 words by 4 bits. The TC514410AP/AJ/ASJ/AZ utilizes TOSHIBA’S CMOS Silicon gate process technology as well as

Contextual Info: PRELIMINARY 4,194,304 WORD x 1 BIT DYNAMIC RAM DESCRIPTION The TC514101AP/AJ/ASJ/AZ is the new generation dynamic RAM organized 4,194,304 words by 1 bit. The TC514101AP/AJ/ASJ/AZ utilizes TOSHIBA’S CMOS Silicon gate process technology as well as advanced circuit techniques to provide wide operating m argins, both internally and to the system user.

A100COLUMN

Contextual Info: 4 ,1 9 4 ,3 0 4 W ORD x 1 BIT D Y N A M IC R A M * This is advanced information and specifica­ tions are subject to change without notice. DESCRIPTION The TC514101AP/AJ/ASJ/AZ is the new generation dynamic RAM organized 4,194,304 words by 1 bit. The TC514101AP/AJ/ASJ/AZ utilizes TOSHIBA’S CMOS Silicon gate process technology as well as

tc51100ap

Abstract: DIP18-P-300E TC514100
Contextual Info: 4,1 94 ,3 0 4 W O R D X PRELIMINARY 1 BIT D Y N A M IC RAM DESCRIPTION The TC514100AF/AJ/ASJ/AZ is the new generation dynamic RAM organized 4,194,304 words by 1 bit. The TC514100AP/AJ/ASJ/AZ utilizes TOSHIBA’S CMOS Silicon gate process technology as well as

KSR128

Abstract: a95x A348 20 pin
Contextual Info: TC514400ÂPL/ÂJL/ASJL/AZL-60 * This is advanced information and specifica­ tions are subject to change without notice. 1,048,576 W ORD x 4 BIT D YN A M IC RAM DESCRIPTION The TC514400APL/AJL/ASJL/AZL is the new generation dynamic RAM organized 1,048,576 words by

TMS44410

Abstract: TMS44410-70
Contextual Info: TMS44410 1 048 576-WORD BY 4-BIT WRITE-PER-BIT DYNAMIC RANDOM-ACCESS MEMORY REV A - • Organization . . . 1 048 576 x 4 SMHS441 JANUARY 1991 DM and DJ Packaget Top View • Single 5-V Power Supply (±10% Tolerance) • Performance Ranges: ACCESS ACCESS ACCESS

TMS44101

Contextual Info: TMS44101 4194 304-BIT DYNAMIC RANDOM-ACCESS MEMORY REV A — SMHS411 — JA N U A R Y 1991 Organization . . . 4 194 304 x DC w C RAS C 1 1 ^ 2 3 Z 4 NC A 10 C 5 Single 5-V Power Supply ±10% Tolerance Performance Ranges: A0 C 9 A1 C 10 A2 C 11 READ ACCESS ACCESS ACCESS

TMS44400

Abstract: TMS44400-10
Contextual Info: TMS44400 1 048 576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY R E V A — S M H S 4 4 0 B — O C T O B E R 1 9 8 9 — R E V IS E D J A N U A R Y 1991 DM AND DJ P acka ge st Top View This Data Sheet Is Applicable to A ll TMS44400s Symbolized With Revision “B" and Subsequent

RENESAS tft application notes

Abstract: R1LV1616R R1LV1616RBG-5S R1LV1616RSA-5S uTSOP
Contextual Info: R1LV1616R Series 16Mb Advanced LPSRAM 1M wordx16bit / 2M wordx8bit REJ03C0101-0300Z Rev.3.00 2007.08.28 Description The R1LV1616R Series is a family of low voltage 16-Mbit static RAMs organized as 1048576-words by 16-bit, fabricated by Renesas's high-performance 0.15um CMOS and TFT technologies.

Contextual Info: 1,048,576 W O R D X 4 BIT D YN A M IC RAM * This is advanced information and specifica­ tions are subject to change without notice. DESCRIPTION The TC514410AP/AJ/ASJ/AZ is the new generation dynamic RAM organized 1,048,576 words by 4 bits. The TC514410AP/AJ/ASJ/AZ utilizes TOSHIBA’S CMOS Silicon gate process technology as well as

Contextual Info: TOSHIBA LOGIC/MEMORY 4,194,304 W O R D X 42E » ^ 7 2 4 0 0 Q 2 0 ci7b T B 1 T 0 S 2 PRELIMINARY 1 "BIT D Y N A M IC R A M 7 - ji. - 2 3 - lS r DESCRIPTION The TC514100AP/AJ/ASJ/AZ is the new generation dynamic RAM organized 4,194,304 words by 1 bit. The TC514100AP/AJ/ASJ/AZ utilizes TOSHIBA’S CMOS Silicon gate process technology as well as

Contextual Info: • li 6 INTEGRATED CIRCUIT TO SH IB A TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT TC51V4400APL / AJ L / A SJ L / A Z L / AFTL / ATRL - 8 0 / 1 0 SILICON GATE CMOS TECH NICAL DATA TENTATIVE D A TA 1.048.576 W ORD x 4 BIT DYN AM IC RAM DESCRIPTION The TC51V4400APL/AJL/ASJL/AZL/AFTL/ATRL is the new generation dynamic RAM organized

AZL-70

Contextual Info: PRELIMINARY 1,048,576 WORD x 4 BIT DYNAMIC RAM DESCRIPTION The TC514400APL/AJL/ASJL/AZL is the new generation dynamic RAM organized 1,048,576 words by 4 bits. The TC514400APL/AJL/ASJL/AZL utilizes TOSHIBA’S CMOS Silicon gate process technology as well as advanced circuit techniques to provide wide operating margins, both internally and to the

n2200

Contextual Info: SHEET 1 OF 1 A 1 23 4 CONTACT CONFIGURATION TIMING BBM NON-SHORTING 14.20 [.559 in] HARDWARE SUPPIED ON SWITCH n26.00 [1.024 in] n6.35 [.250 in] 10.00 [.394 in] PIN 9 FOR SUPPORT ONLY . 5 0 n] 27 83 i .0 [1 5.50 [.217 in] FLAT 3/8-32 UNEF-2A THREADS 2.00

M514400a

Abstract: M514400 L06lC ZP-20S
Contextual Info: blE H M D • 44TL5D3 GD22774 SOñ 5 1 4 4 0 0 A / A L / A S L S e r i e s — 1,048,576-word X4-bit Dynamic RAM HITACHI/ The Hitachi HM514400A/AL/ASL is a CMOS dynamic RAM organized 1,048,576-word x 4-bit. HM514400A/AL/ASL has realized higher density, higher perform ance and various functions by

Contextual Info: SHEET 1 OF 1 A 1 2 3 4 CONTACT CONFIGURATION TIMING BBM NON-SHORTING 14.20 [.559 in] 1.20 [.047 in] X 1.5 DEEP n26.20 [1.031 in] 8.00 [.315 in] ISOMETERIC 2.00 [.079 in] HARDWARE SUPPIED ON SWITCH ACTUATOR FLUSH WITH BUSHING . 50 n ] 27 83 i .0 [1 3/8-32 UNEF-2A

Contextual Info: SHEET 1 OF 1 A 1 2 3 4 5 6 7 8 9 101112 CONTACT CONFIGURATION TIMING BBM SHORTING HARDWARE SUPPIED ON SWITCH n26.20 [1.031 in] 14.20 [.559 in] 8.00 [.315 in] 2.00 [.079 in] 7.00 [.276 in] .50 n] 27 83 i .0 [1 M10X0.75 THREADS 2.00 [.079 in] 19.00 [.748 in]

Contextual Info: SHEET 1 OF 1 A 1 2 3 4 5 6 7 8 9101112 CONTACT CONFIGURATION TIMING BBM NON-SHORTING 14.20 [.559 in] HARDWARE SUPPIED ON SWITCH n26.00 [1.024 in] 8.00 [.315 in] n6.35 [.250 in] 13.00 [.512 in] . 50 n ] 27 83 i .0 [1 5.50 [.216 in] FLAT 3/8-32 UNEF-2A THREADS

PLC18V8ZIAA

Contextual Info: Product specification Philips Semiconductors Programmable Logic Device Products Zero standby power CMOS versatile PAL devices PLC18V8Z25/PLC18V8ZIA PIN CONFIGURATIONS DESCRIPTION FEATURES The PLC18V8Z is a universal PAL device featuring high performance and virtually

Contextual Info: SHEET 1 OF 1 A C 12 3 7 8 9 CONTACT CONFIGURATION TIMING MBB SHORTING 14.20 [.559 in] HARDWARE SUPPIED ON SWITCH 2.00 [.079 in] 8.00 [.315 in] n26.00 [1.024 in] 30.00 [1.181 in] .5 n ] 27 83 i .0 [1 30.0° n3.00 [.118 in] 3/8-32 UNEF-2A THREADS 2.00 [.079 in]

Contextual Info: SHEET 1 OF 1 A 1 4 7 10 CONTACT CONFIGURATION TIMING BBM NON-SHORTING 14.20 [.559 in] HARDWARE SUPPIED ON SWITCH 8.00 [.315 in] n26.20 [1.031 in] 2.00 [.079 in] 13.00 [.512 in] .50 n] 27 83 i .0 [1 n6.35 [.250] 5.50 [.217 in] FLAT 2.00 [.079 in] 3/8-32 UNEF-2A

Contextual Info: SHEET 1 OF 1 A 1 23 4 56 78 9 CONTACT CONFIGURATION TIMING BBM NON-SHORTING 14.20 [.559 in] HARDWARE SUPPIED ON SWITCH 8.00 [.315 in] n26.00 2.00 [.079 in] ISOMETERIC [1.024 in] 10.00 [.394 in] . 5 n] 27 83 i .0 [1 3/8-32 UNEF-2A THREADS n3.00 2.00 [.079 in]

Contextual Info: SHEET 1 OF 1 A 1 2 3 CONTACT CONFIGURATION TIMING BBM NON-SHORTING HARDWARE SUPPIED ON SWITCH n26.20 [1.031 in] 18.00 [.709 in] . 50 n ] 27 83 i .0 [1 14296 REV PCR NO ISOMETRIC 10.00 [.394 in] n6.00 [.236 in] 3/8-32 UNEF-2A THREADS 2.00 [.079 in] NOTE:

Contextual Info: SHEET 1 OF 1 A C 12 3 7 8 9 CONTACT CONFIGURATION TIMING MBB SHORTING 14.20 [.559 in] HARDWARE SUPPIED ON SWITCH 2.00 [.079 in] 8.00 [.315 in] n26.00 [1.024 in] 30.00 [1.181 in] .5 n ] 27 83 i .0 [1 n6.35 [.250] 5.50 [.217 in] FLAT n3.00 [.118 in] 30.0°