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Vishay Dale CMF5539K200FHEB RES 39.2K OHM 1/2W 1% AXIAL
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CMF5539K200FHEB	Cut Tape	5,806		1	1 $0.63 10 $0.359 100 $0.2142 1000 $0.15434 10000 $0.15434	Buy Now
	CMF5539K200FHEB	Reel	5,000		1,000	1 - 10 - 100 - 1000 $0.13533 10000 $0.09829	Buy Now
RS	CMF5539K200FHEB	Bulk			1,000	1 - 10 - 100 - 1000 $0.107 10000 $0.107	Get Quote
Vishay Dale CMF6039K200FKEA RES 39.2K OHM 1W 1% AXIAL
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CMF6039K200FKEA	Cut Tape	2,460		1	1 $0.86 10 $0.492 100 $0.2958 1000 $0.18889 10000 $0.18889	Buy Now
Vishay Dale CMF5039K200FHEB RES 39.2K OHM 1/4W 1% AXIAL
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CMF5039K200FHEB	Cut Tape	1,748		1	1 $1.49 10 $0.862 100 $0.5276 1000 $0.3882 10000 $0.3882	Buy Now
	CMF5039K200FHEB	Reel	1,000		1,000	1 - 10 - 100 - 1000 $0.3438 10000 $0.3438	Buy Now
Vishay Dale CMF5539K200FKEK RES 39.2K OHM 1/2W 1% AXIAL
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CMF5539K200FKEK	Bulk	100		1	1 $7.57 10 $4.577 100 $2.9314 1000 $2.9314 10000 $2.9314	Buy Now
Vishay Dale CMF5539K200FHEK RES 39.2K OHM 1/2W 1% AXIAL
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CMF5539K200FHEK	Bulk	95		1	1 $2.23 10 $1.324 100 $0.9494 1000 $0.9494 10000 $0.9494	Buy Now
RS	CMF5539K200FHEK	Bulk			100	1 - 10 - 100 $1.14 1000 $1.14 10000 $1.09	Get Quote

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39K200 Datasheets (1)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
39K200		Cypress Semiconductor	CPLDs at FPGA Densities		Original	PDF

39K200 Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
Untitled Abstract: No abstract text available Text: Delta39K ISR™ CPLD Family CPLDs at FPGA Densities™ Features • Carry-chain logic for fast and efficient arithmetic operations • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+	Original	Delta39Kâ 64-bit 39K200-208EQFP 39K165 39K200 -233MHz Delta39K165Z 144-FBGA	PDF
laptop ac adapter schematics diagram Abstract: laptop adapter circuit by delta electronics schematic led video colour display colour television schematics Panasonic color television schematic diagram laptop led screen cable block diagram pe-65508 schematic of rgb led video wall TPS3820-33 schematic diagram catv receiver satellite Text: HOTLink II Video Evaluation Board Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 September 18, 2003, rev. 0.A [+] Feedback HOTLink II™ Video Evaluation Board Table of Contents 1.0 Introduction . 5	Original		PDF
vhdl code for dice game Abstract: Video Proc 3.3V 0.07A 64-Pin PQFP ez811 GRAPHICAL LCD interfaced with psoc 5 cypress ez-usb AN2131QC CYM9239 vhdl code PN 250 code generator CY3649 cy7c63723 Keyboard and Optical mouse program CY7C9689 ethernet Text: Product Selector Guide Communications Products Description Pins Part Number Freq. Range Mbps ICC (mA) Packages* 3.3V SONET/SDH PMD Transceiver 2.5V SiGe Low Power SONET/SDH Transceiver SONET/SDH Transceiver w/ 100K Logic 2.5 G-Link w/ 100K Logic OC-48 Packet Over SONET (POS) Framer	Original	OC-48 CYS25G0101DX CYS25G0102 CYS25G01K100 CYP25G01K100 CY7C9536 CY7C955 CY7B952 CY7B951 10BASE vhdl code for dice game Video Proc 3.3V 0.07A 64-Pin PQFP ez811 GRAPHICAL LCD interfaced with psoc 5 cypress ez-usb AN2131QC CYM9239 vhdl code PN 250 code generator CY3649 cy7c63723 Keyboard and Optical mouse program CY7C9689 ethernet	PDF
484-FBGA Abstract: 484FBGA 256-FBGA LB 1 39K250 Text: Delta39K ISR™ CPLD Family ADVANCE INFORMATION CPLDs at FPGA Densities™ • Multiple I/O standards supported — LVCMOS, LVTTL, PCI, SSTL, HSTL, and GTL+ • Compatible with NOBL™, ZBT™, and QDR™ SRAMs • Programmable slew rate control on each I/O pin	Original	Delta39KTM 64-bit 484-FBGA 484FBGA 256-FBGA LB 1 39K250	PDF
84 FBGA Abstract: 39K100 39K200 39K30 39K50 388-BGA Text: Delta39K ISR™ CPLD Family CPLDs at FPGA Densities™ Features • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+ • Compatible with NOBL™, ZBT™, and QDR™ SRAMs	Original	Delta39KTM 66-MHz 64-bit 39K165 208-EQFP, 484-FBGA, 388-BGA, 676-FBGA 84 FBGA 39K100 39K200 39K30 39K50 388-BGA	PDF
bga rework Abstract: 39K200 39K100 39K165 39K30 39K50 WT2-56 Text: Family, Package, and Density Migration in Delta39K and Quantum38K™ CPLDs Introduction I. Family Migration The Delta39K™ and Quantum38K™ family of Complex Programmable Logic Devices CPLDs combine dense logic, embedded memory, and configurable I/O standards. Further design flexibility is added by the easy migration options available	Original	Delta39KTM Quantum38KTM bga rework 39K200 39K100 39K165 39K30 39K50 WT2-56	PDF
8kx1 RAM Abstract: No abstract text available Text: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ Features • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+ • Compatible with NOBL™, ZBT™, and QDR™ SRAMs	Original	Delta39KTM 233-MHz MIL-STD-883" /JESD22A114-A 39K50 39K30 Delta39K 39K165/200 CY3LV002 CY3LV020. 8kx1 RAM	PDF
39k200 Abstract: CY39200V Text: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ Features •Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+ •Compatible with NOBL™, ZBT™, and QDR™ SRAMs	Original	Delta39KTM 250-MHz 39k200 CY39200V	PDF
2M X 32 Bits 72-Pin Flash SO-DIMM Abstract: AN2131QC Triton P54C SO-DIMM 72pin 32bit 5V 2M AN2131-DK001 AN2131SC vhdl code for pipelined matrix multiplication VIC068A user guide parallel interface ts vhdl 7C037 Text: GO TO WEB MAIN INDEX 3URGXFW 6HOHFWRU *XLGH Static RAMs Organization/Density Overview Density X1 X4 X8 X9 X16 X18 X32 X36 7C148 7C149 7C150 4 Kb 16 Kb 7C167A 7C168A 7C128A 6116 64 Kb to 72 Kb 7C187 7C164 7C166 7C185 6264 7C182 256 Kb to 288 Kb 7C197 7C194	Original	7C148 7C149 7C150 7C167A 7C168A 7C128A 7C187 7C164 7C166 7C185 2M X 32 Bits 72-Pin Flash SO-DIMM AN2131QC Triton P54C SO-DIMM 72pin 32bit 5V 2M AN2131-DK001 AN2131SC vhdl code for pipelined matrix multiplication VIC068A user guide parallel interface ts vhdl 7C037	PDF
CY39100V484B-125BBI Abstract: programmable slew rate control IO AT17LV010-10JI CY39030V256-125MBC IO1 5V 39K100 39K165 39K30 39K50 CY39100V208B-125NTC Text: Delta39K ISR™ CPLD Family CPLDs at FPGA Densities™ Features • Carry-chain logic for fast and efficient arithmetic operations • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+	Original	Delta39KTM 66-MHz 64-bit 39K165 MG388 CY39030 -256FBGA CY39100V484B-125BBI programmable slew rate control IO AT17LV010-10JI CY39030V256-125MBC IO1 5V 39K100 39K30 39K50 CY39100V208B-125NTC	PDF
39K100 Abstract: 39K30 39K50 Text: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ Features — Clock polarity control at each register • Carry-chain logic for fast and efficient arithmetic operations • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2	Original	Delta39KTM 64-bit 39K200-208EQFP 39K165 39K200 -233MHz Delta39K165Z 39K100 39K30 39K50	PDF
CY39200V Abstract: No abstract text available Text: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ •Multiple I/O standards supported — LVCMOS, LVTTL, 3.3V PCI, SSTL2 I-II , SSTL3 (I-II), HSTL (I-IV), and GTL+ •Compatible with NOBL™, ZBT™, and QDR™ SRAMs •Programmable slew rate control on each I/O pin	Original	Delta39KTM NT208 51-85069-B 388-Lead MG388 256-Ball BB256/MB256 1-85108-A CY39200V	PDF
delta39k Abstract: 39K100 39K30 39K50 Text: Delta39K ISR™ CPLD Family CPLDs at FPGA Densities™ Features • Carry-chain logic for fast and efficient arithmetic operations • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+	Original	Delta39KTM 64-bit 39K165 MG388 CY39030 -256FBGA delta39k 39K100 39K30 39K50	PDF
ATDH2225 Abstract: CD74LPT244 39K100 39K165 39K30 39K50 AT17 AT40K AT94K EPF10K Text: Description The configurator in-system programming cable ISP cable is a PC-only based cable that attaches to the parallel port of a computer. This cable can be used to download and verify configuration data cascading up to 8 devices. This cable allows designers to	Original	05/01/xM ATDH2225 CD74LPT244 39K100 39K165 39K30 39K50 AT17 AT40K AT94K EPF10K	PDF

bga 484 0.8mm pitch Abstract: 20532 tqfp 39K100 39K200 39K30 39K50 484FBGA CY39200V208-181NTXC CY39100V208B-125NTxC cy39030v208-125ntxc Text: Delta39K ISR™ CPLD Family CPLDs at FPGA Densities™ Features • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+ • Compatible with NOBL™, ZBT™, and QDR™ SRAMs	Original	Delta39KTM 66-MHz 64-bit 39K165 208-EQFP, 484-FBGA, 388-BGA, 676-FBGA bga 484 0.8mm pitch 20532 tqfp 39K100 39K200 39K30 39K50 484FBGA CY39200V208-181NTXC CY39100V208B-125NTxC cy39030v208-125ntxc	PDF
CY39100V484-125BBI Abstract: "Single-Port RAM" delta39k Text: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ •Multiple I/O standards supported — LVCMOS, LVTTL, 3.3V PCI, SSTL2 I-II , SSTL3 (I-II), HSTL (I-IV), and GTL+ •Compatible with NOBL™, ZBT™, and QDR™ SRAMs •Programmable slew rate control on each I/O pin	Original	Delta39KTM CY39100V484-125BBI "Single-Port RAM" delta39k	PDF
NT208 Abstract: 1kx8 rom 250NTC Text: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ •Carry-chain logic for fast and efficient arithmetic operations •Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+	Original	Delta39KTM 250-MHz NT208 1kx8 rom 250NTC	PDF