MM74C30N
Abstract: MM54C30J MM74C30 MM54C30 MM74C30J AN-90 C1995 J14A
Text: MM54C30 MM74C30 8-Input NAND Gate General Description Features The logical gate employs complementary MOS CMOS to achieve wide power supply operating range low power consumption and high noise immunity Function and pin out compatibility with series 54 74 devices minimizes design
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MM54C30
MM74C30
MM74C30N
MM54C30J
MM74C30J
AN-90
C1995
J14A
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PO74G10A
Abstract: No abstract text available
Text: PO74G10A www.potatosemi.com TRIPLE 3-INPUT POSITIVE-NAND GATES 54, 74 Series Noise Cancellation GHz Logic FEATURES: DESCRIPTION: . Patented technology . Operating frequency up to 1GHz with 2pf load . Operating frequency up to 800MHz with 5pf load . Operating frequency up to 350MHz with 15pf load
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PO74G10A
800MHz
350MHz
14pin
150mil
PO74G10A
PO74G10ASU
POTATO74G10AS
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74 series
Abstract: Potato Semiconductor 74 Series Logic ICs CERAMIC LEADLESS CHIP CARRIER A115-A C101 PO54G00A PO74G00A PO74G00ASR PO74G00ASU
Text: PO54G00A, PO74G00A QUADRUPLE 2-INPUT POSITIVE-NAND GATE 09/12/07 54, 74 Series GHz Logic FEATURES: DESCRIPTION: . Patented technology . Specified From –40°C to 85°C, –40°C to 125°C, and –55°C to 125°C . Operating frequency up to 1.125GHz with 2pf load
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PO54G00A,
PO74G00A
125GHz
750MHz
350MHz
2000-VHuman-BodyModel
A114-A)
200-VMachineModel
A115-A)
1000-VCharged-DeviceModel
74 series
Potato Semiconductor
74 Series Logic ICs
CERAMIC LEADLESS CHIP CARRIER
A115-A
C101
PO54G00A
PO74G00A
PO74G00ASR
PO74G00ASU
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PO74G00A
Abstract: No abstract text available
Text: PO54G00A, PO74G00A www.potatosemi.com QUADRUPLE 2-INPUT POSITIVE-NAND GATE 54, 74 Series Noise Cancellation GHz Logic FEATURES: DESCRIPTION: . Patented technology . Specified From –40°C to 85°C, –40°C to 125°C, and –55°C to 125°C . Operating frequency up to 1.125GHz with 2pf load
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PO54G00A,
PO74G00A
125GHz
750MHz
350MHz
5000-VHuman-BodyModel
A114-A)
200-VMachineModel
A115-A)
14pin
PO74G00A
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TSSOP14
Abstract: 74hc132y
Text: M74HC132 Quad 2-input Schmitt NAND gate Datasheet - production data • Wide operating voltage range: VCC opr = 2 V to 6 V • Pin and function compatible with 74 series 132 SO14 TSSOP14 • ESD performance – HBM: 2 kV – MM: 200 V – CDM: 1 kV Description
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M74HC132
TSSOP14
M74HC132
M74HC00.
DocID1896
TSSOP14
74hc132y
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7430N
Abstract: FJH101 FJH101A fjh-101 6430N D1110 FJH106 H101
Text: T.T.L. SINGLE 8-INPUT NAND GATES FIHIOI FJHIOIA Correspond to 74 Series types 7430N, 6430N FJHI06 TENTATIVE DATA These devices are tran sistor-tran sistor logic single 8-input NAND gates in the FJ s e r ie s of integrated c ircu its. The FJH101 corresponds to '74 Series' type 7430N,
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7430N,
6430N
FJH106
FJH101
FJH106
6430N.
FJH101/1A
O-116
7430N
FJH101A
fjh-101
D1110
H101
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AND-OR-INVERT gate
Abstract: 74 series family 74 series inverter
Text: BIPOLAR DIGITAL ICs continued •o 4->a 5 D Q. • PACKAGE C FANOUT DESCRIPTION TYPE TTL-T 74 H, T 54 H series" T 74/54 H 00 Quad 2-input positive NAND gate 6 90 10 T 74/54 H 04 Hex inverter 8 140 10 DIP H,P DIP H,P T 74/54 H 05* Hex inverter w ith open collector
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74/-OR-INVERTER
range-55
AND-OR-INVERT gate
74 series family
74 series inverter
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Untitled
Abstract: No abstract text available
Text: LS TTL DN74LS Series DN74LS22 DN74LS22 bio 74.LS Q Dual 4-input P ositive NAND Gates with Open Collector Outputs • Description P-1 DN74LS22 contains two 4-input positive isolation NAND gate circuits w ith open collector outputs. ■ Features • • •
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DN74LS
DN74LS22
DN74LS22
14-pin
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Untitled
Abstract: No abstract text available
Text: DM9003C fjWA National J u i Semiconductor \ DM9003C Triple 3-Input NAND Gates General Description For the new designs, the 54/74 fam ilies o f TTL c ircu its o f fer the industry's broadest choice of high-performance d igita l circuits. Series 54/74 pin-for-pin equivalent is
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DM9003C
DM9003C
9000-type
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MA161
Abstract: DN74LS38 s0140
Text: L S T T L DN74LS Series DN74LS38 D N 74LS38 bM 74- L-S S'? Quad 2-input P ositive NAND B u ffers with Open C ollector Outputs • Description D N 74LS38 contains four 2-input positive isolation NAND buffer gate circuits with open collector outputs. P-1 H Features
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DN74LS
DN74LS38
DN74LS38
14-pin
S0-140)
MA161
s0140
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DN74LS20
Abstract: MA161
Text: LS T T L DN74LS Series DN74LS20 DN74LS20 5 rO 74 U 5U3 Dual 4 - input P o sitiv e NAND Gates H Description P-1 DN74LS20 contains two 4-input positive isolation NAND gate circuits. I Features • • • • Low power consumption Pd = 4m W typical High speed (tpd = 10ns typical)
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DN74LS
DN74LS20
DN74LS20
14-pin
SO-14D)
DN741S20
CL-15pF,
MA161
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7410N
Abstract: 2 input nand gate 24v FJH121 FJH121A 121-Page 6410N FJH106 FJH126 2 input nor gate 24v
Text: FIHI2I FJHI2IA T.T.L. TRIPLE 3-INPUT NAND GATES Correspond to 74 Series types 7410N, 6410N FJHI26 TENTATIVE DATA T hese d e v ic es a re tr a n s is to r - tr a n s is to r logic tr ip le 3-input NAND g ates in the F J s e r ie s of in te g rate d c ir c u its . The FJH121 c o rre sp o n d s to '74 S e rie s ' type 7410N,
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7410IM,
6410N
FJHI26
FJH121
7410N,
FJH126
6410N.
FJH121/1A
O-116
7410N
2 input nand gate 24v
FJH121A
121-Page
FJH106
2 input nor gate 24v
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7410N
Abstract: pin diagram for all 74 series ttl gates FJH121 6410N FJH121A 74 series logic gates ttl NAND gate circuit FJH106 FJH126 NAND Gates
Text: T.T.L. TRIPLE 3-INPUT NAND GATES FIHI2I FJH I2IA Correspond to 74 Series types 7410N, 6410N FJHI26 TENTATIVE DATA T hese d e v ic es a re tr a n s is to r - tr a n s is to r logic tr ip le 3-input NAND g ates in the F J s e r ie s of in te g rate d c ir c u its . The FJH121 c o rre sp o n d s to '74 S e rie s ' type 7410N,
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7410IM,
6410N
FJHI26
FJH121
7410N,
FJH126
6410N.
FJH121/1A
O-116
7410N
pin diagram for all 74 series ttl gates
FJH121A
74 series logic gates
ttl NAND gate circuit
FJH106
NAND Gates
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Untitled
Abstract: No abstract text available
Text: UNITED MICROELECTRONICS 0e! .9325812 ÏÊ| 1325012 0000200 Q | U N ITED MICROELECTRONICS 890 00288 U A 1300 SERIES |Gate Arrays } = Features • Silicon-gate 2.0 micron drawn double metal HCMOS technology. ■ Speeds higher than 74/TT L-1.7ns through 2-input NAND gate and interconnection,
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74/TT
UA1313
UA1318
UA1322
UA1330
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SN7439
Abstract: n5439
Text: TYPES SN5439, SN7439 QUADRUPLE 2-INPUT POSITIVE NAND BUFFERS WITH OPEN-COLLECTOR OUTPUTS REVISED M A V 1983 SN5439 . J PACKAG E Current Sinking Capability up to 80 mA SN7439 . J OR N PACKAG E Guaranteed Fan-Out of 30 Series 54/74 Loads ÎT O P V IEW
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SN5439,
SN7439
SN5439
n5439
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DN74LS40
Abstract: MA161
Text: LS T T L DN74LS Series DN74LS40 DN74LS40 [O-74.LS4 Dual 4 - input P o sitiv e N AN D B uffers • Description P-1 DN 74LS40 contains tw o 4-input positive isolation NAND b u ffer gate circuits. ■ Features • • • • High fan-out IOL = 24m A , IOH = - 1 ,2m A
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DN74LS
DN74LS40
DN74LS40
14-pin
SO-14D)
MA161
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7403N
Abstract: pin diagram for all 74 series ttl gates FJH291 FJH291A nor gate 24v supply FJH29I
Text: T.T.L. QUADRUPLE 2-INPUT POSITIVE NAND GATES FJH29I FJH29IA Corresponds to 74 Series type 7403N PR O V ISIO N A L DATA T hese d evices a r e tr a n s is to r - tr a n s is to r logic quadruple 2-input p o sitiv e NAND g a te s, w ith a single-ended open c o lle cto r output tra n s is to r , in the F J s e r ie s of in te g rate d
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FJH29I
FJH29IA
7403N
FJH291
7403N.
O-116
FJH291-Page
B9B01
7403N
pin diagram for all 74 series ttl gates
FJH291A
nor gate 24v supply
FJH29I
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74 LS 00 Nand Gates
Abstract: No abstract text available
Text: LS T T L DN74LS Series DN74LS26 DN74LS26 J>M 74 l -i 2^ Quad 2 - input High-Voltage Interface P ositive NAND Gates I Description D N 7 4 L S 2 6 c o n ta in s b u ffe r gate c irc u its. P-1 fo u r 2 -in p u t p o sitiv e iso la tio n N A N D I Features •
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DN74LS
DN74LS26
14-pin
SO-14DI
CL-15pF,
74 LS 00 Nand Gates
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Untitled
Abstract: No abstract text available
Text: SN5439, SN7439 QUADRUPLE 2-INPUT POSITIVE NAND BUFFERS WITH OPEN COLLECTOR OUTPUTS MAY • SN 5439. SN 7439 C urrent Sinking Capability up to 80 m A G uaranteed Fan-O ut of 30 Series 54/74 Loads • i y C 1 1A C 988 . J P AC KA G E N P AC KA G E i b These devices contain four independent 2-input NA ND
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SN5439,
SN7439
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DN74LS22
Abstract: No abstract text available
Text: LS TTL DN74LS Series DN74LS22 DN741S22 bio 74. l S Q 2^ Dual 4-input P ositive NAND Gates with Open Collector Outputs • Description P-1 D N 7 4 L S 2 2 c o n ta in s tw o 4 -in p u t p o sitiv e is o la tio n N A N D gate c irc u its w ith o p e n c o lle c to r o u tp u ts .
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DN74LS
DN741S22
DN74LS22
14-pin
SO-14D)
CL-15pF,
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ha 1452
Abstract: 7401N FJH231A truth table NAND gate 74 FJH231 ft 5777 2 input nor gate 24v Transistor B 1566
Text: FJH23I FJH23IA T.T.L. QUADRUPLE 2-INPUT POSITIVE N A N D GATES Corresponds to 74 Series type 7401N TEN TA TIV E DATA T hese dev ices a re tr a n s is to r - tr a n s is to r logic quadruple 2-input positive NAND g a te s , with a sin g le-en d ed open c o lle cto r output t r a n s is to r , in the F J s e r ie s of in te g rate d
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FJH23I
FJH23IA
7401N
FJH231
7401N.
FJH231-Page
B9801
ha 1452
7401N
FJH231A
truth table NAND gate 74
ft 5777
2 input nor gate 24v
Transistor B 1566
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7400N
Abstract: 2 input nand gate 24v D1113 FJH131 FJHI36 6400N FIH131 FJH131A FJH136 2 input nor gate 24v
Text: T.T.L. QUADRUPLE 2-INPUT NAND GATES Correspond to 74 Series types 7400N, 6400N FIH13 1 FJHI3IA FJHI36 T ENTATIVE DATA T h e s e d e v ic e s a r e t r a n s i s t o r - t r a n s i s t o r lo g ic q u a d ru p le 2 -in p u t NAND g a te s in th e F J s e r i e s of in te g r a te d c i r c u i t s . T h e F JH 131 c o r r e s p o n d s to '7 4 S e r i e s 't y p e 7400N,
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FIH131
7400N,
6400N
FJHI36
FJH131
FJH136
6400N.
FJH131/1A
7400N
2 input nand gate 24v
D1113
FJHI36
FIH131
FJH131A
2 input nor gate 24v
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7401AN
Abstract: FJH311 FJH311A pin diagram for all 74 series ttl gates transistor KJJ
Text: T.T.L. Q U A D R U P L E 2 -IN P U T P O S IT IV E N A N D G A T E S F IH 3 M F J H 3 IIA Corresponds to 74 Series type 7401AN PR O V IS IO N A L D A T A T hese dev ices a r e t r a n s is to r - tr a n s is to r logic quadruple 2-input p o sitiv e NAND g a te s ,
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7401AN
FJH311
7401AN.
FJH311-Page
7401AN
FJH311A
pin diagram for all 74 series ttl gates
transistor KJJ
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16-LINE TO 4-LINE PRIORITY ENCODERS
Abstract: 74 series logic gates Flip flops "J-K Flip flops" J-K Flip flops NAND Gates HD74 Synchronous 8-Bit Binary Counters HD74S synchronous binary counter with latch
Text: o V o la i \ \_ a . TTL H D 74/H D 74S Series I M A IN C HARACTERISTICS I PERFORMANCE (per gate Performance HD74 Series HD74S Series Propagation 10 ns 3 ns Delay Time Power 10 mW 20 m\V Dissipation Speed-Power 100 pJ 60 pJ Product O Series Param eter max)
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HD74/HD74S
HD74S
HD74Series
16-bit
DP-14
DP-16
DP-20
16-LINE TO 4-LINE PRIORITY ENCODERS
74 series logic gates
Flip flops
"J-K Flip flops"
J-K Flip flops
NAND Gates
HD74
Synchronous 8-Bit Binary Counters
synchronous binary counter with latch
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