74LVX74

Abstract: 74LVX74M 74LVX74MTR 74LVX74TTR TSSOP14
Contextual Info: 74LVX74 LOW VOLTAGE CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR 5V TOLERANT INPUTS • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED : fMAX = 145MHz (TYP.) at VCC = 3.3V 5V TOLERANT INPUTS INPUT VOLTAGE LEVEL : VIL=0.8V, VIH=2V AT VCC=3V LOW POWER DISSIPATION:

74LVX74

Abstract: 74LVX74MTR 74LVX74TTR TSSOP14
Contextual Info: 74LVX74 LOW VOLTAGE CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR 5V TOLERANT INPUTS • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 145MHz (TYP.) at VCC = 3.3V 5V TOLERANT INPUTS INPUT VOLTAGE LEVEL: VIL=0.8V, VIH=2V AT VCC=3V LOW POWER DISSIPATION:

LVX74

Abstract: 74LVX74SJ M14A 74LVX74 74LVX74M 74LVX74MTC M14D MTC14
Contextual Info: Revised December 2003 74LVX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop General Description Asynchronous Inputs: The LVX74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary Q, Q outputs. Information at the input is transferred to the outputs on the

dn 101

Contextual Info: 998 S E M IC O N D U C T O R tm 74LVX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop Clear and Set are independent of clock General Description The LVX74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary Q, Q outputs. Informa­

LVX74

Abstract: 74LVX74 74LVX74M 74LVX74MTC 74LVX74SJ M14A M14D MTC14
Contextual Info: 74LVX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop Features General Description • Input voltage level translation from 5V to 3V The LVX74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary Q, Q outputs. Information at the input is transferred to the outputs on

Contextual Info: S E M [CONDUCTOR TM 74LVX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop General Description The LVX74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary Q, Q outputs. Information at the input is transferred to the outputs on the

74LVX74

Abstract: 74LVX74M 74LVX74MTC 74LVX74SJ LVX74 M14A M14D MTC14
Contextual Info: EMICDNDUCTOR t 74LVX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop General Description C lear and Set are independent of clock The LVX74 is a dual D-type flip-flop w ith Asynchronous C lear and Set inputs and com plem entary Q, Q outputs. Inform a­

74LVX74

Abstract: 74LVX74M 74LVX74MTR 74LVX74TTR TSSOP14
Contextual Info: 74LVX74 LOW VOLTAGE CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR 5V TOLERANT INPUTS • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED : fMAX = 145MHz (TYP.) at VCC = 3.3V 5V TOLERANT INPUTS INPUT VOLTAGE LEVEL : VIL=0.8V, VIH=2V AT VCC=3V LOW POWER DISSIPATION:

74LVX74

Abstract: 74LVX74M 74LVX74MTC 74LVX74SJ LVX74 M14A M14D MTC14
Contextual Info: 74LVX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop General Description The LVX74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary Q, Q outputs. Information at the input is transferred to the outputs on the positive

74LVX74

Abstract: 74LVX74M 74LVX74MTC 74LVX74SJ LVX74 M14A M14D MTC14
Contextual Info: 74LVX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop General Description The LVX74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary Q, Q outputs. Information at the input is transferred to the outputs on the positive

74LVX74

Abstract: 74LVX74M 74LVX74MTR 74LVX74TTR TSSOP14
Contextual Info: 74LVX74  LOW VOLTAGE DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR • ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 145 MHz TYP. at VCC = 3.3V INPUT VOLTAGE LEVEL: VIL = 0.8V, VIH = 2V at VCC = 3V LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA = 25 oC

IL52

Abstract: LVX74 CT-501 74LVX74 74LVX74M 74LVX74MTC 74LVX74MTCX 74LVX74MX 74LVX74SJ 74LVX74SJX
Contextual Info: X > N ational Semiconductor 74LVX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop General Description Features The LVX74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary Q, Q outputs. Information at the input is transferred to the outputs on the

74LVX74

Contextual Info: 74LVX74 LOW VOLTAGE CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR 5V TOLERANT INPUTS • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 145MHz (TYP.) at VCC = 3.3V 5V TOLERANT INPUTS INPUT VOLTAGE LEVEL: VIL=0.8V, VIH=2V AT VCC=3V LOW POWER DISSIPATION:

Contextual Info: 74LVX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop Features General Description • Input voltage level translation from 5V to 3V The LVX74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary Q, Q outputs. Information at the input is transferred to the outputs on

74LVX74

Abstract: 74LVX74M 74LVX74MTC 74LVX74MTCX 74LVX74MX 74LVX74SJ 74LVX74SJX LVX74 M14A M14D
Contextual Info: 74LVX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop General Description Features The LVX74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary Q Q outputs Information at the input is transferred to the outputs on the

74LVX74

Abstract: 74LVX74M 74LVX74MTC 74LVX74SJ LVX74 M14A M14D MTC14
Contextual Info: Revised March 1999 74LVX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop General Description Asynchronous Inputs: The LVX74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary Q, Q outputs. Information at the input is transferred to the outputs on the

LVX74

Contextual Info: LVX74 EHSemiconductor National 74LVX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop General Description Features The LVX74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary Q, (5 outputs. Information at the input is transferred to the outputs on the

74LVX74

Abstract: 74LVX74M 74LVX74MTC 74LVX74MTCX 74LVX74SJ LVX74 M14A M14D MTC14
Contextual Info: Revised February 2005 74LVX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop General Description The LVX74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary Q, Q outputs. Information at the input is transferred to the outputs on the

master slave jk flip flop

Abstract: ECL D flip flop Flip Flop DIP Flip flop JK cmos 74lvt16374 d flip flop d type flip flop flip flop flip flop circuit flip flop circuit type D
Contextual Info: Logic Products by Function Flip-Flop Products Logic Product Family Product Description Package Voltage Node 74ACT109 FACT ACT Dual JK Positive Edge-Triggered Flip-Flop DIP SOIC TSSOP 5 DM74LS73A Bipolar-LS Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary

TTL 74-series IC LIST

Abstract: 74 Series Logic ICs TTL 74-series IC PO74G74 PO74G04 list cmos ics 49fct32805 49FCT3807 Potato Semiconductor 49FCT3805
Contextual Info: 04/18/07 Pin to Pin & Package to Package Compatible IC List Standard 1.65V -3.6 V TTL / CMOS Clock Buffer PotatoSemi PO49FCT3802A 1GHz 1 to 5 PO49FCT3803B 700MHz 1 to 7 PO49FCT3804 800MHz 2X1 to 4 PO49FCT3805B 800MHz 2X1 to 5 PO49FCT3806 750MHz 2X1 to 5 PO49FCT3807B

5555 FAIRCHILD optocoupler

Abstract: MC74HC374N 74hc14n equivalent NC7S125M5 14069 HCF4541BEY APPLICATION HCF4013BE 4026 fairchild datasheet 14543 motorola Motorola DM74LS139N
Contextual Info: R E L I A B L E . L O G I C . I N N O V A T I O N . Logic Cross-Reference Logic Cross-Reference 2003 Texas Instruments Printed in the U.S.A. by Texoma Business Forms, Durant, Oklahoma Printed on recycled paper. SCYB017A NEW First Revision Logic Cross-Reference

74LVT JK Flip Flop

Abstract: led driver SOT23 6pin lcx244 MOTOROLA lcx 4245 LCX244 quad single supply 50 Ohm Line Drivers diode sj Fairchild Power Switch package to 220 p5 MAX 16841 On semiconductor LCX 574 PA
Contextual Info: 1 Chapter 1 Introduction to Low-Voltage Logic Chapter C R O S S V O L T Parts & Availability 17 Packaging Options 37 Low-Voltage Logic Cross Reference 49 Glossary 57 Fairchild Low-Voltage Logic Reference Guide Chapter Chapter Glossary  Introduction to Low-Voltage Logic

Contextual Info: ALPHANUMERICAL INDEX LCX FAMILY Type Number Function Package Page Number 51 74LCX00 Quad 2-Input NAND Gate with 5V Tolerant Input TSS0P/S014 74LCX02 Quad 2-Input NOR Gate with 5V Tolerant Input TSS0P/S014 57 74LCX04 Hex Inverter with 5V Tolerant Input TSS0P/S014

schematic diagram atx Power supply 500w

Abstract: pioneer PAL 012A 1000w inverter PURE SINE WAVE schematic diagram 600va numeric ups circuit diagrams winbond bios 25064 TLE 9180 infineon smsc MEC 1300 nu TBE schematic diagram inverter 2000w DK55 circuit diagram of luminous 600va UPS
Contextual Info: QUICK INDEX NEW IN THIS ISSUE! Detailed Index - See Pages 3-24 Digital Signal Processors, iCoupler , iMEMS® and iSensor . . . . . 805, 2707, 2768-2769 Connectors, Cable Assemblies, IC Sockets . . . . . . . . . . . 28-568 RF Connectors . . . . . . . . . . . . . . . . . . . . . . Pages 454-455