74ALS09

Abstract: SN54ALS09 SN74ALS09
Contextual Info: ü • a d S' SN 54A LS09, SN 74ALS09 QUADRUPLE 2 INPUT POSITIVE AND GATES WITH OPEN COLLECTOR OUTPUTS D 2 6 6 1 , A P R IL 1 9 8 2 - R E V IS E D M A Y 1 9 8 6 Package Options Include Plastic "Sm all Outline" Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-m il

Contextual Info: MITSUBISHI ALSTTLs M 74ALS1035P TËJ MITSUB ISH I {DGTL LOGIC} Q012732 G | HEX NONINVERTING BUFFER W ITH OPEN COLLECTOR OUTPUT / DESCRIPTION PIN CONFIGURATION TOP VIEW ” T h e M 7 4 A L S 1 0 3 5 P is a s e m ic o n d u c to r in te g ra te d c ir­ c u it c o n s is tin g o f six n o n -inverting b u ffe rs w ith open

ci la 7610

Contextual Info: c +e MITSUBISHI ALSTTLs . op,00° M 74A L S 620A -1P v ie N v t ^s ^ - 3 _ OCTAL BUS TRANSCEIVER W ITH 3-STATE OUTPUT INVERTED 6249827 MITSUBISHI CDGTL LOGIC) DESCRIPTION The M74ALS6Í20A-1P is a semiconductor integrated cir­ cuit consisting of eight bus transm itter/receiver circuits

ci la 7610

Contextual Info: MITSUBISHI ALSTTLs M 7 4 A LS 6 5 1 P 7 -52-3/ OCTAL BUS TRANSCEIVER/REGISTER W ITH 3-STATE OUTPUT INVERTED 6249827 MITSUBISHI 91 D 12674 (DGTL LOGIC ) DESCRIPTION The M74ALS651P is a semiconductor integrated circuit consisting of eight bus transceiver/registers with 3-state

Contextual Info: MITSUBISHI íDGTL LOGICI TI DEI't.E4*1ñ27 D0ia3flD S MITSUBISHI ALSTTLs M 624 9 82 7 M IT S U B IS H I DG TL L O G IC 7 4 A 91D L S 1 1 3 A P 12380 D DUAL J-K N EG A TIVE EDGE-TRIGGERED FLIP -FLO P W IT H SET T -H (* -o 7 -o y DESCRIPTION PIN CONFIGURATION (TOP VIEW)

m74als191p

Contextual Info: ÍDGTL LOGIC} 91D TI De | 12446 b241fl27 □ 0 1 2 4 4b ñ r D MITSUBISHI ALSTTLs M 74A LS191P SYNCHRONOUS PRESETTABLE UP/DOWN 4 -B IT BINARY COUNTER W ITH MODE CONTROL • 7 ^ V ' 5 ' ' ^ >3 DESCRIPTION - o 7 PIN CONFIGURATION TOP VIEW Th e M 7 4 A L S 1 9 1 P is a s e m ic o n d u c to r in te g ra te d c irc u it

74ALS640

Contextual Info: MITSUBISHI -CDGTL LOGIC} dT | ba^flS? D O i a k b B 4 M ITSUBISHI A L ST T Ls sc* -s s 5 " : . M 7 4 A LS6 4 7 P ,o.9B OCTAL BUS TR A N SC EIV ER /R EG IST ER WITH OPEN COLLECTOR OUTPUT NONINVERTED 6249827 MITSUBISHI CDGTL LOGTC) DESCRIPTION The M74ALS647P is a semiconductor integrated circuit

Contextual Info: MITSUBISHI ALSTTLs M 7 4 A L S 1 0 0 2 À P a D eE| tk24=]aS7 0015712 > | MITSUBISHI IDGTL LOGIC} 11 QUADRUPLE 2-IN P U T PO SITIVE NOR BUFFER 7 ^ V 3 - /S DESCRIPTION PIN CONFIGURATION (TOP VIEW) The M74ALS1002AP is a semiconductor integrated cir­ cuit consisting of four 2-input positive-logic NOR buffer

J 5027 R

Abstract: BEM 6K
Contextual Info: MIT SUBISH I íDGTL L O G I C } T I d ËT| ^5^027 ~JZ.SZt~3/ G0127SS □ MITSUBISHI ALSTTLs M 74A L S 1621A P I 62 49 8 2 7 M I T S U B I S H T T D G T L T o G r ^ ~ 910 12755 D OCTAL BUS TRANSCEIVER W ITH OPEN COLLECTOR OUTPUT NONINVERTED) DESCRIPTION

Contextual Info: MITSUBISHI -CDGTL L O G I O TI DE | bSMTfla? 001E4b4 □ M IT SU B ISH I ALSTTLs M74ALS241AP 6249827 MITSUBISHI DGTL LOGIC 91D 12464 D O CTAL B U F F E R /L IN E D R IV E R W IT H 3 -ST A T E O U T PU T (N O N IN V E R T E D ) DESCR IPTIO N The M74ALS241AP is a semiconductor integrated circuit

Contextual Info: MITSUBISHI ALSTTLs & M74ALS169BP T ' - v ’S '- J J - o SYNCHRONOUS PRESETTABLE UP/DOWN 4 -B IT BINARY COUNTER 6249827 MITSUBISHI DG TL LOGIC DESCRIPTION Th e M 74A L S 169 B P is a sem iconductor integrated circuit of a synchronous p resettable u p /d o w n

74als561

Contextual Info: MITSUBISHI íDGTL LOGIC} "DÌI bSMTñE? 00123ki7 5 TI W~ M IT S U B IS H I* !L. S T T L s M74ALS38AP 91D 12367 D 6249827 MITSUBISHI DGTL LOGIC QUADRUPLE 2 -IN P U T P O S ITIV E NAND BUFFER W IT H OPEN COLLECTOR OU TPUT T - - V 3 - / S DESCRIPTION PIN CONFIGURATION (TOP VIEW)

Contextual Info: "d ë J M ITS UBISHI -CDGTL L O G I O bEMTfla? ooiBS'in a S^Ls MITSUBISHI ALSTTLs M 74ALS133P r _ 6249827 MITSUBISHI - y j - / r SINGLE 13-IN PU T POSITIVE NAND GATE DGTL LOGIC DESCRIPTION Th e M 7 4A LS 133P is a sem iconductor integrated circuit

m74als

Abstract: M74ALS109AP 74ALS640
Contextual Info: M IT S U B IS H I {D G T l T o G IcT ^ I b H 1 SS? M 6249827 MITSUBISHI 7 4 A CDGTL LOGIC 91D J STTLs L S 1 0 9 A 12 37 4 P D DUAL J-R POSITIVE EDGE-TRIGGERED FLIP-FLOP W ITH SET AND RESET T -V & -0 7 - Ô ? DESCRIPTION PIN CONFIGURATION TOP VIEW) The M74ALS109AP is a semiconductor Integrated circuit

M74ALS1032AP

Contextual Info: MITSUBISHI ALSTTLs M 74ALS1 0 3 2 AP M I T S U B I S H I - C D G T L L O G I C } T I D È I ” L ^ M ^ ñ S ? 1 2 7 5 fi QUADRUPLE 2-IN P U T POSITIVE OR BUFFER _ DESCRIPTION _ _ _ _ PIN CONFIGURATION TOP VIEW The M74ALS1032AP is a semiconductor integrated cir­

74LS38-74AS38

Abstract: X3-131-1986 74ls387 74LS327 82258 NCR SCSI Siemens 82258
Contextual Info: inte1 I/O BOARD SPECIFICATION SUMMARY iSBC 386/258 PERIPHERAL CONTROLLER CPU DMA DRAM EPROM SCSI Device Support Transfer Rate Serial I/O Ports Timers/Counters iSBX IEEE P959 Backplane Connectors Compatible Drives: Hard Disks Tape Drive Adapters Power Requirements

74ALS573AD

Abstract: 74ALS574AD
Contextual Info: M ITSUBISHI ALSTTLs r M 7 4 A L S 1 6 4 5 A P D e | bSMTfla? DDia77T 3 MITSUBISHI -CDGTL LOGIC} OCTAL BUS TR A N SC EIVER W IT H 3-STATE O U TPUT N O N IN VERTED - 7 “' » DESCRIPTION The M74ALS1645AP is a semiconductor integrated cir­ cuit consisting of eight bus transmitter/receiver circuits

c 2274

Contextual Info: '7 ' '0 7 -0 5 * MITSUBISHI ALSTTLs OCTAL D -TY P E EDGE-TRIGGERED FLIP-FLO P W IT H 3-S TA TE O U TPU T N O N IN V E R TE D . Ä > a 6249827 M IT S U B IS H I (D G TL L O G IC ) DESCRIPTION consisting o f eight D-type positive edge-triggered flipflop circuits w ith 3-state noninverted output and is pro­

74ALS273P

Abstract: M74ALS273P
Contextual Info: MITSUBISHI -CDGTL LOGIC} TI D e B bSMTñE? DDIHSDI 5 MITSUBISHI ALSTTLs M 74A LS273P T z- / ù > ~ o y - < o s ' OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP FLOP WITH RESET 9 1D 12501 6249827 MITSUBISHI ÍDGTL LOgT c T DESCRIPTION PIN CONFIGURATION TOP VIEW

Contextual Info: MITSUBISHI ALSTTLs M74ALS623AP MITSUBISHI O G T L LOGIC} bSMTflS? DOiabS? 2 OCTAL BUS TRANSCEIVER W ITH 3-STATE OUTPUT INONINVEBTED 7 ’" - 5 2 - 3 / DESCRIPTION The M74ALS623AP is a semiconductor integrated circuit consisting of eight bus transm itter/receiver circuits with

dd127

Abstract: 74ALS640 74ALS138DP 74ALS374DW ci la 7610 74als642 74als245a 74ALS245ADW 74als561 M74ALS04
Contextual Info: n i T S U B I S H I -CDGTL L O G IC } tiE T l a 57 O G l^ t^ b | MITSUBISHI ALSTTLs M 74A LS40A P 6 2 4 9 8 2 7 M T T s U B r S H F T M fr T Ö G r c T - 9 1 0 1 2 3 6 9 D DUAL 4-IN P U T POSITIVE NAND BUFFER 7 DESCRIPTION - - * /3 - tT/ PIN CONFIGURATION TOP VIEW

74ALS131

Abstract: 74ALS573AD
Contextual Info: 7 = ^ ce v -y -0 7 ' -^ S ' MITSUBISHI ALSTTLs M 74ALS874AP .< „c X '8n DUAL 4 -B IT D -T Y P E EDGE-TRIGGERED FLIP-FLO P _ W IT H 3 -S T A T E O U TPU T N O N IN V E R T E D 0249827 MITSUBISHI ÌOGTL LOGIC) DESCRIPTION The M 74ALS874AP Is a sem iconductor integrated circuit

74als520

Abstract: dd127
Contextual Info: MITSUBISHI -CDGTL LOGIC* TI ^F|t.SMTñ27 0015543 7 J ~ MITSUBISHI ALSTTLs & M 74A LS519P > ^ vA" 0\ 7 ^ .V «" / 5 e / ' 7 8-BIT MAGNITUDE COMPARATOR WITH OPEN COLLECTOR OUTPUT 9 1D 12543 6249827 MITSUBISHI DGTL LOGIC DESCRIPTION Th e M 7 4 A L S 5 1 9 P is a sem iconductor integ rated circuit

74ALS643

Contextual Info: MITSUBISHI ALSTTLs M 74A L S 643A P MITSUBISHI -CDGTL LOGIC} TI D E I bSMTÖE? 0012t,4b b OCTAL BUS TRANSCEIVER W ITH 3-STATE OUTPUT DESCRIPTION PIN CONFIGURATION TOP VIEW The M74ALS643AP is a semiconductor integrated circuit consisting of eight bus transm itter/receiver circuits with