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    74LVC3GU04DP Search Results

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    74LVC3GU04DP Price and Stock

    Nexperia 74LVC3GU04DP,125

    IC INVERTER 3CH 3-INP 8TSSOP
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    DigiKey 74LVC3GU04DP,125 Cut Tape 5,975 1
    • 1 $0.47
    • 10 $0.332
    • 100 $0.2574
    • 1000 $0.21819
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    74LVC3GU04DP,125 Digi-Reel 5,975 1
    • 1 $0.47
    • 10 $0.332
    • 100 $0.2574
    • 1000 $0.21819
    • 10000 $0.21819
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    74LVC3GU04DP,125 Reel 3,000 3,000
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    Avnet Americas 74LVC3GU04DP,125 Reel 8 Weeks 6,000
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    Mouser Electronics 74LVC3GU04DP,125 1,057
    • 1 $0.47
    • 10 $0.297
    • 100 $0.239
    • 1000 $0.219
    • 10000 $0.193
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    Newark 74LVC3GU04DP,125 Cut Tape 1,735 1
    • 1 $0.68
    • 10 $0.564
    • 100 $0.427
    • 1000 $0.288
    • 10000 $0.288
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    TTI 74LVC3GU04DP,125 Reel 6,000
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    • 10000 $0.174
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    TME 74LVC3GU04DP,125 1,216 3
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    • 10 $0.253
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    Avnet Asia 74LVC3GU04DP,125 8 Weeks 6,000
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    • 10000 $0.19934
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    Avnet Silica 74LVC3GU04DP,125 10 Weeks 3,000
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    EBV Elektronik 74LVC3GU04DP,125 10 Weeks 3,000
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    NXP Semiconductors 74LVC3GU04DP,125

    Inverter 3-ElementCMOS 8-Pin TSSOP T/R
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Verical 74LVC3GU04DP,125 51,000 2,025
    • 1 -
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    • 10000 $0.1853
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    Rochester Electronics 74LVC3GU04DP,125 51,000 1
    • 1 $0.1743
    • 10 $0.1743
    • 100 $0.1638
    • 1000 $0.1482
    • 10000 $0.1482
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    74LVC3GU04DP Datasheets (7)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    74LVC3GU04DP NXP Semiconductors Triple unbuffered inverter Original PDF
    74LVC3GU04DP Philips Semiconductors 74LVC3GU04, Triple inverter Original PDF
    74LVC3GU04DP,125 NXP Semiconductors 74LVC3GU04 - IC LVC/LCX/Z SERIES, TRIPLE 1-INPUT INVERT GATE, PDSO8, 3 MM, PLASTIC, SOT-505-2, TSSOP-8, Gate Original PDF
    74LVC3GU04DP125 NXP Semiconductors NOW NEXPERIA 74LVC3GU04DP INVERT Original PDF
    74LVC3GU04DP,125 NXP Semiconductors Triple inverter - Description: 3.3V Triple PicoGate Inverter unbuffered ; Logic switching levels: TTL ; Number of pins: 8 ; Output drive capability: +/- 32 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 2.6@3.3V ns; Voltage: 1.65-5.5; Package: SOT505-2 (TSSOP8); Container: Reel Pack, Reverse, Reverse Original PDF
    74LVC3GU04DP-G NXP Semiconductors 74LVC3GU04DP - Triple inverter - Description: 3.3V Triple PicoGate Inverter unbuffered ; Logic switching levels: TTL ; Number of pins: 8 ; Output drive capability: +/- 32 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 2.6@3.3V ns; Voltage: 1.65-5.5 Original PDF
    74LVC3GU04DP-G NXP Semiconductors Triple inverter - Description: 3.3V Triple PicoGate Inverter unbuffered ; Logic switching levels: TTL ; Number of pins: 8 ; Output drive capability: +/- 32 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 2.6@3.3V ns; Voltage: 1.65-5.5 Original PDF

    74LVC3GU04DP Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: 74LVC3GU04 Triple inverter Rev. 10 — 6 July 2012 Product data sheet 1. General description The 74LVC3GU04 provides three inverters. Each inverter is a single stage with unbuffered output. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of


    Original     		PDF 74LVC3GU04 74LVC3GU04 JESD22-A114F JESD22-A115-A

    mnb120

    Abstract: No abstract text available
    Text: 74LVC3GU04 Triple inverter Rev. 01 — 12 May 2004 Product data sheet 1. General description The 74LVC3GU04 is a high-performance, low-power, low-voltage, Si-gate CMOS device superior to most advanced CMOS compatible TTL families. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these


    Original     		PDF 74LVC3GU04 74LVC3GU04 EIA/JESD22-A114-B EIA/JESD22-A115-A mnb120

    74LVC3GU04

    Abstract: 74LVC3GU04DC 74LVC3GU04DP 74LVC3GU04GM 74LVC3GU04GT JESD22-A114E MO-187 VU04
    Text: 74LVC3GU04 Triple inverter Rev. 06 — 4 March 2008 Product data sheet 1. General description The 74LVC3GU04 provides three inverters. Each inverter is a single stage with unbuffered output. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of


    Original     		PDF 74LVC3GU04 74LVC3GU04 JESD8B/JESD36 JESD22-A114E JESD22-A115-A 74LVC3GU04DC 74LVC3GU04DP 74LVC3GU04GM 74LVC3GU04GT MO-187 VU04

    Untitled

    Abstract: No abstract text available
    Text: 74LVC3GU04 Triple inverter Rev. 9 — 23 November 2011 Product data sheet 1. General description The 74LVC3GU04 provides three inverters. Each inverter is a single stage with unbuffered output. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of


    Original     		PDF 74LVC3GU04 74LVC3GU04 JESD22-A114F JESD22-A115-A

    Untitled

    Abstract: No abstract text available
    Text: 74LVC3GU04 Triple unbuffered inverter Rev. 11 — 9 April 2013 Product data sheet 1. General description The 74LVC3GU04 is a triple unbuffered inverter. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.


    Original     		PDF 74LVC3GU04 74LVC3GU04 JESD22-A114F JESD22-A115-A

    74LVC3GU04GD

    Abstract: 74LVC3GU04 74LVC3GU04DC 74LVC3GU04DP 74LVC3GU04GM 74LVC3GU04GT VU04 sot833-1 marking nxp TSSOP8 package
    Text: 74LVC3GU04 Triple inverter Rev. 07 — 11 November 2009 Product data sheet 1. General description The 74LVC3GU04 provides three inverters. Each inverter is a single stage with unbuffered output. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of


    Original     		PDF 74LVC3GU04 74LVC3GU04 JESD8B/JESD36 JESD22-A114F JESD22-A115-A 74LVC3GU04GD 74LVC3GU04DC 74LVC3GU04DP 74LVC3GU04GM 74LVC3GU04GT VU04 sot833-1 marking nxp TSSOP8 package

    VU04

    Abstract: 74LVC3GU04 74LVC3GU04DC 74LVC3GU04DP 74LVC3GU04GM 74LVC3GU04GT JESD22-A114E MO-187
    Text: 74LVC3GU04 Triple inverter Rev. 05 — 5 October 2007 Product data sheet 1. General description The 74LVC3GU04 provides three inverters. Each inverter is a single stage with unbuffered output. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of


    Original     		PDF 74LVC3GU04 74LVC3GU04 JESD8B/JESD36 JESD22-A114E JESD22-A115-A VU04 74LVC3GU04DC 74LVC3GU04DP 74LVC3GU04GM 74LVC3GU04GT MO-187

    Untitled

    Abstract: No abstract text available
    Text: 74LVC3GU04 Triple inverter Rev. 02 — 27 October 2004 Product data sheet 1. General description The 74LVC3GU04 is a high-performance, low-power, low-voltage, Si-gate CMOS device superior to most advanced CMOS compatible TTL families. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these


    Original     		PDF 74LVC3GU04 74LVC3GU04 JESD8-B/JESD36

    VU04

    Abstract: 74LVC3GU04 74LVC3GU04DC 74LVC3GU04DP 74LVC3GU04GD 74LVC3GU04GM 74LVC3GU04GT MNB120
    Text: 74LVC3GU04 Triple inverter Rev. 8 — 10 November 2010 Product data sheet 1. General description The 74LVC3GU04 provides three inverters. Each inverter is a single stage with unbuffered output. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of


    Original     		PDF 74LVC3GU04 74LVC3GU04 JESD22-A114F JESD22-A115-A VU04 74LVC3GU04DC 74LVC3GU04DP 74LVC3GU04GD 74LVC3GU04GM 74LVC3GU04GT MNB120

    VU04

    Abstract: 74LVC3GU04 74LVC3GU04DC 74LVC3GU04DP 74LVC3GU04GT MO-187
    Text: 74LVC3GU04 Triple inverter Rev. 03 — 01 February 2005 Product data sheet 1. General description The 74LVC3GU04 is a high-performance, low-power, low-voltage, Si-gate CMOS device superior to most advanced CMOS compatible TTL families. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these


    Original     		PDF 74LVC3GU04 74LVC3GU04 VU04 74LVC3GU04DC 74LVC3GU04DP 74LVC3GU04GT MO-187

    Untitled

    Abstract: No abstract text available
    Text: 74LVC3GU04 Triple inverter Rev. 10 — 6 July 2012 Product data sheet 1. General description The 74LVC3GU04 provides three inverters. Each inverter is a single stage with unbuffered output. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of


    Original     		PDF 74LVC3GU04 74LVC3GU04 JESD22-A114F JESD22-A115-A

    Untitled

    Abstract: No abstract text available
    Text: 74LVC3GU04 Triple inverter Rev. 04 — 15 March 2007 Product data sheet 1. General description The 74LVC3GU04 is a high-performance, low-power, low-voltage, Si-gate CMOS device superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of


    Original     		PDF 74LVC3GU04 74LVC3GU04 JESD8B/JESD36