777T Search Results

NJU6395

Contextual Info: NJU6395v&#39;J-X w NJU6395v&#39;J-X* i t . » 125IIHzS-Cï3IÎSTOÎEfi«Œ*MÎ *a£JS fflC-MOS ICT*. f t l & m T j 1 \ NJU6395y&#39;J-rii, A, h7^T-hA*777T#lfi£iF3|iS'fo •£*1-Ç*i80~ 110MHz, 105~125MHz Z fiÜJÎ><pJÎÎÊT'-fo liNAND»a-C361iff±lSG) >fi*«3tibSli3b'o-C

Contextual Info: www.teleqqertner.com Fax: +49 7157 125-120 31.8 Phone: +49 7157 125-0 13 777T > W ro oo csj I D— 71144 Steinenbronn LerchenstraBe 35 Germany CO Cu2Ni5 Cu1Ni2Au0.8 AuBenleiter / outer conductor Innenleiter / inner conductor Isolerung / insulator Crimprohr / crimp ferrule

ic tea 1090

Abstract: HJU6375IE NJU6375 NJU6375XC CI tl 464 TEA 1090
Contextual Info: Egg HJUB375i^ U - X ic m m , m NJU6375&#39;> ' - X i . 75MHz t X 'S £ iS ^ # 6 4 '* ifl3 g iif flC - M O S IC i>7<77-h^'777Ti«?hit. %mmr>-7, x, MJU6375 > 'J — (¿20— 35MHz, A . B . C & U U J, K0) 6 « * lX * « j ic £ f t . A £ H Bt J(i3 0 ~ 5 0 M H z, C t Kti45~ 75M H zO Tf£iJS A< °T

2SC3644

Abstract: 777T
Contextual Info: O rd e rin g n u m b e r: EN 1628C N0.1628C 2SC3644 NPN Triple Diffused Planar Silicon Transistor Ultrahigh-Definition Display Horizontal Deflection Output Applications i oi i— Features • High reliability Adoption of HVP process . • High speed. • High breakdown voltage.

SMD W2T

Abstract: w2t smd BTS 131 SMD MBA IST DATE SHEET SN54ACT3632
Contextual Info: • fl^bi723 aiiossT ist. ■ SN54ACT3632 512x36x2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY _ _ S G B S310-SEPTEM BER 1996 * Free-Running CLKA and CLKB Can Be Asynchronous or Coincident ► Two Independent 512 x 36 Clocked FIFOs

Contextual Info: First-In First-Out FIFO 64x4 64x5 Memory 15 MHz (Cascadable) C67L401D C67L402D Ordering Inform ation Features/ Benefits • High-speed 15-MHz shift-in/shift-oul rates • Low power consumption PART NUMBER PKG TEMP DESCRIPTION • Choice of 4-bit or 5-bit data width

Contextual Info: H D 4 0 7 4 0 0 8 HMCS400 SERIES ZTAT MICROCOMPUTER Pin Arrangem ent Description T h e H D 4 0 7 4 0 0 8 is a m ass-storage ZTAT™ m icro­ com puter incorporating 8K w ords of program ­ m able ROM and 512 d igits of R A M . It is a CM O S 4-bit sin gle-ch ip H M C S 400-series m icrocom puter

ir911

Abstract: A14C A15C A25C A26C SN74ACT3631 SN74ACT3641 SN74ACT3651
Contextual Info: SN74ACT3641 1024x36 CLOCKED FIRST-IN, FIRST-OUT MEMORY S CAS338A - JANUARY 1994 - RE V IS E D JUNE 1994 Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A to Port B Memory Size: 1024 x 36 Synchronous Read Retransmit Capability

CX10047

Abstract: sony CX10047 CX10045 CX10046 ccd sony sony CX10045 SONY CAMERA BW82 cx10047 sony
Contextual Info: mutœutam* h M .jft»-. •. ri—" ■ lliiTMt SONY CORP/COMPONENT PRODS 7? D e | 0302303 DDDQ30M T I D T - 7 7-/7 CX10045 CCD CAMERA SIGNAL PROCESSING WITH SAMPLE-HOLD CIRCUIT Description: C X 10045 is a bipolar 1C designed for CCD camera signal processing. It samples the CCD image

Contextual Info: 10 0.6 TW A /4\ 10 .2 5 F P C JTAYES 3 .6 (A) INSERTION DEPTH OF FPC | 0 .5 | - I A A L Y 1 _ I t f (PITCH) LENGTH TO CONTACT POINT S W A P ( ± B ) _ CONTACT POINT (UPPER SIDE) (6 .5 5 ) Y A T A D L /R 1 Y S 1 ) (WHEN ACTUATOR IS OPENED)

STK-083G

Abstract: STK IC Sanyo STK STK SANYO STK-083
Contextual Info: STK-083G s $ # * # S A N Y O • “ a No.746 1IÓ0 * - 40W m in A &■ •# X vcc max «m w t> y ór 6 “ T -A rtJ j/. ±d6 Iwí — 30'" ^S tg cc = z t 3 2 V ^ | [ = 8 Q , .# ' /' / P 0 = d O W tf^ Ü H a ßx$t ±yf/ v // Ù .of> vcc Rl *JJ m * l ± / Ta = 2 5 * C , Vc c = ± 32V,

AM9517A

Abstract: AM53C80N AM5380 processor VIA C7-D
Contextual Info: Am5380/Am53C80N* SCSI Interface Controller DISTINCTIVE CHARACTERISTICS SCSI Interface • • • • • • CPU Interface Asynchronous interface to 1.5 megabytes per second Supports Initiator and Target roles Parity generation with optional checking Supports Arbitration

tney2

Abstract: HM5241 5241605
Contextual Info: HM5241605 Series 131,072-word x 16-bit x 2-bank Synchronous Dynamic RAM HITACHI A ll inputs and outputs are referred to the rising edge of the clock input. The HM5241605 is offered in 2 banks for improved performance. _ F e a tu re s •3.3V Power s u p p

B86605

Contextual Info: Ê S S P C o m m u n tc a tío n C o n tro l CMOS • DESCRIPTION The MB86606 is an intelligent SCSI protocol controller SPC conforming to ih ANSI (FAST-20) standard and integrating a PCI local bus interface function. The specification of S C S i controller block is based on the

CC-3802

Abstract: CC-3851 CC-3801 777t CC-3852 CC-3853 TDK CC-3801
Contextual Info: TDK DC to DC Converters, DC to AC Inverters 250mW T D K CORP . $ 40E m ô ô2154fl oooqcjc^ fl B T1>KA t . s v -h C C S E R IES D C TO DC C O N V E R T E R S M T T F O F 2 M IL L IO N H O U R S Th e C C series developed to provide - 5 , - 1 2 , - 1 5 , +12, +15Vdc voltage conversion from 5Vdc lines.

Contextual Info: Integrated Devile Technology, lie. CMOS TRIPLE BUS SyncFIFOT WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 FEATURES: • Two independent FIFOs 64 X 36 storage capacity each buffer data between bidirectional 36-bit port A and two unidirectional 18/9-bit ports (Port B transmits, Port C

Contextual Info: THBT7011D Application Specific Discretes A DUAL O VERVO LTAG E PRO TECTIO N FOR TELECOM LINE PR ELIM IN ARY DATASHEET FEATURES • BIDIRECTIONAL CROWBAR PROTECTION. ■ PEAK PULSE CURRENT : lp p = 3 0 A fo r 10/1000|j,s surge. ■ HOLDING C URRENT: Ih = 150mA.

Nippon capacitors

Abstract: MC12061 sine wave crystal controlled oscillator 145191
Contextual Info: Order this document byMC145190/D MOTOROLA H SEMICONDUCTOR TECHNICAL DATA Product Preview ^ MC145190 MC145191 1.1 GHz PLL Frequency Synthesizers • M Ü i i Î M i Include On-Board 64/65 Prescalers The MC145190 and MC145191 are single-package synthesizers with serial inter­

NSK 4.096

Abstract: qml-38535 GDIP4-T28 BFR.L
Contextual Info: REVISIONS DATE DESCRIPTION LTR APPROVED YR-MO-DA REV SHEET REV SHEET 15 16 17 REV STATUS OF SHEETS 18 19 20 21 22 23 24 REV 8 SHEET PREPARED BY Jeff Bowling PMIC N/A STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE

LM 8512

Abstract: T4C marking marking t4c
Contextual Info: ADVANCE M T4C 8512/3 S 512K x 8 W IDE DRAM M IC R O N WIDE DRAM 512K x 8 DRAM FEATURES PIN ASSIGNMENT Top View • Industry-standard x8 pinouts, timing, functions and packages • Address entry: ten row-addresses, nine columnaddresses • High-perform ance CM O S silicon-gate process

MPA-S-112-A 12V

Abstract: SP5502F
Contextual Info: MITEL SP5502 1.3GHz l2C BUS 4-Address Synthesiser S E M IC O N D U C T O R Supersedes version in April 1994 Consum er IC Handbook, HB3120 - 2.0 for TV tuning systems. Control data is entered in the standard

Contextual Info: 3.3 VOLT CMOS SyncBiFlFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 PRELIMINARY IDT72V3614 ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ Three modes of byte-order swapping on port B Programmable Almost-Full and Almost-Empty flags Microprocessor interface control logic

SM5605F

Abstract: SM5605FA SM5605FC 555 NC
Contextual Info: SM5605F OJPC LSI for Quartz Crystal Oscillating Module NIPPON PRECISION CIRCUITS INC. • OVERVIEW The SM5605F series are C-MOS LSIs for quartz oscillating module. Each LSI has a high frequency oscillating circuit and dividers with low current consumption. One of the output

upd4265

Abstract: 4265 AAFW
Contextual Info: SEC /iP D 4 2 6 5 6 5 ,5 3 6 x 1 -B IT D Y N A M IC CMOS RAM NEC Electronics Inc. Revision 1 Pin Configuration D e scrip tio n T h e N E C /UPD4265 is a 6 5 ,5 3 6 -w o rd b y 1 -b it d y n a m ic C M O S R a n d o m A c c e s s M e m o ry R A M d e s ig n e d to