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    onsemi NB7L11MMN

    IC CLK BUFFER 1:2 8GHZ 16QFN
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    Flip Electronics NB7L11MMNG

    IC CLK BUFFER 1:2 8GHZ 16QFN
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    DigiKey NB7L11MMNG Tube 15
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    onsemi NB7L11MMNG

    IC CLK BUFFER 1:2 8GHZ 16QFN
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    Avnet Americas NB7L11MMNG Tube 0 Weeks, 2 Days 20
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    Rochester Electronics NB7L11MMNG 2,122 1
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    Velocity Electronics NB7L11MMNG 58
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    Flip Electronics NB7L11MMNG 13,335
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    Rochester Electronics LLC NB7L11MMNG

    IC CLK BUFFER 1:2 8GHZ 16QFN
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    DigiKey NB7L11MMNG Bulk 8
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    onsemi NB7L11MMNR2

    IC CLK BUFFER 1:2 8GHZ 16QFN
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    DigiKey NB7L11MMNR2 Reel 3,000
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    7L11M Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    NB6N11SMNG

    Abstract: No abstract text available
    Text: NB6N11S 3.3 V 1:2 AnyLevelE Input to LVDS Fanout Buffer / Translator Description The NB6N11S is a differential 1:2 Clock or Data Receiver and will accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These signals will be translated to LVDS and two identical


    Original
    PDF NB6N11S NB6N11S/D NB6N11SMNG

    Untitled

    Abstract: No abstract text available
    Text: NB4N11S 3.3 V 1:2 AnyLevel Input to LVDS Fanout Buffer / Translator The NB4N11S is a differential 1:2 Clock or Data Receiver and will accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These signals will be translated to LVDS and two identical


    Original
    PDF NB4N11S NB4N11S/D

    485G

    Abstract: EP11 NB4N11S
    Text: NB4N11S 3.3 V 1:2 AnyLevel Input to LVDS Fanout Buffer / Translator The NB4N11S is a differential 1:2 Clock or Data Receiver and will accept AnyLevelTM input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These signals will be translated to LVDS and two


    Original
    PDF NB4N11S NB4N11S NB4N11S/D 485G EP11

    NB6N11S/D, August, 2009 Rev. 5

    Abstract: 485G EP11 NB6N11S
    Text: NB6N11S 3.3 V 1:2 AnyLevelE Input to LVDS Fanout Buffer / Translator Description The NB6N11S is a differential 1:2 Clock or Data Receiver and will accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These signals will be translated to LVDS and two identical


    Original
    PDF NB6N11S NB6N11S NB6N11S/D NB6N11S/D, August, 2009 Rev. 5 485G EP11

    Untitled

    Abstract: No abstract text available
    Text: NB6N11S 3.3 V 1:2 AnyLevelE Input to LVDS Fanout Buffer / Translator Description The NB6N11S is a differential 1:2 Clock or Data Receiver and will accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These signals will be translated to LVDS and two identical


    Original
    PDF NB6N11S NB6N11S/D

    Untitled

    Abstract: No abstract text available
    Text: NB6N11S 3.3 V 1:2 AnyLevelE Input to LVDS Fanout Buffer / Translator Description The NB6N11S is a differential 1:2 Clock or Data Receiver and will accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These signals will be translated to LVDS and two identical


    Original
    PDF NB6N11S NB6N11S NB6N11S/D

    485G

    Abstract: EP11 NB6N11S
    Text: NB6N11S 3.3 V 1:2 AnyLevelE Input to LVDS Fanout Buffer / Translator Description The NB6N11S is a differential 1:2 Clock or Data Receiver and will accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These signals will be translated to LVDS and two identical


    Original
    PDF NB6N11S NB6N11S NB6N11S/D 485G EP11

    Untitled

    Abstract: No abstract text available
    Text: NB4N11M 3.3 V 2.5 Gb/s Multi Level Clock/Data Input to CML Receiver/ Buffer/ Translator Description T h e N B 4 N 11 M i s a d i f f e r e n t i a l 1 −t o −2 c l o c k / d a t a distribution/translation chip with CML output structure, targeted for high−speed clock/data applications. The device is functionally


    Original
    PDF NB4N11M LVEP11, 7L11M NB4N11M NB4N11M/D

    7L11M

    Abstract: EP11 NB4N11M
    Text: NB4N11M 3.3 V 2.5 Gb/s Multi Level Clock/Data Input to CML Receiver/ Buffer/ Translator Description T h e N B 4 N 11 M i s a d i f f e r e n t i a l 1 −t o −2 c l o c k / d a t a distribution/translation chip with CML output structure, targeted for high−speed clock/data applications. The device is functionally


    Original
    PDF NB4N11M LVEP11, 7L11M NB4N11M NB4N11M/D EP11

    485G

    Abstract: EP11 NB6N11S NB6N11SMNG 7L11M 15LVDS
    Text: NB6N11S 3.3 V 1:2 AnyLevelE Input to LVDS Fanout Buffer / Translator Description The NB6N11S is a differential 1:2 Clock or Data Receiver and will accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These signals will be translated to LVDS and two identical


    Original
    PDF NB6N11S NB6N11S NB6N11S/D 485G EP11 NB6N11SMNG 7L11M 15LVDS