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    Intel Corporation NT80960KB-20

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    Intel Corporation NG80960KB20STD

    EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT RISC Microprocessor, 32-Bit, 20MHz, CMOS, PQFP132
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    ComSIT USA NG80960KB20STD 5
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    80960KB Datasheets (5)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    80960KB Intel EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT Original PDF
    80960KB Intel EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT Original PDF
    80960KB-16 Intel 32-bit Cpu, 512 Instruction Cache, 4 Interrupts, Dma, Fpu Original PDF
    80960KB-20 Intel 32-bit Cpu, 512 Instruction Cache, 4 Interrupts, Dma, Fpu Original PDF
    80960KB-25 Intel Processor, EMBEDDED 32 Bit MICROPROCESSOR With INTEGRATED FLOATING-POINT UNIT Original PDF

    80960KB Datasheets Context Search

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    TA80960kb

    Abstract: NG80960KB-25 80960KA 80960KB 80960MC
    Text: 80960KB 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT • High-Performance Embedded ■ Built-in Interrupt Controller Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache


    Original     		PDF 80960KB 32-BIT 512-Byte 132-Lead 80960KB TA80960kb NG80960KB-25 80960KA 80960MC

    TA80960KB

    Abstract: LAD1 5V Intel 80960kb programmers reference 80960KA 80960KB 80960MC Intel 80960kb
    Text: 80960KB 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT • High-Performance Embedded ■ Built-in Interrupt Controller Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache


    Original     		PDF 80960KB 32-BIT 512-Byte 132-Lead 80960KB TA80960KB LAD1 5V Intel 80960kb programmers reference 80960KA 80960MC Intel 80960kb

    TA80960KB

    Abstract: 80960KA 80960KB 80960MC LAD1 12v
    Text: 80960KB 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT • High-Performance Embedded ■ Built-in Interrupt Controller Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache


    Original     		PDF 80960KB 32-BIT 512-Byte 132-Lead 80960KB TA80960KB 80960KA 80960MC LAD1 12v

    TA80960KB

    Abstract: ADS-132 80960KA 80960KB 80960MC LAD26
    Text: 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped


    Original     		PDF 80960KB 32-BIT 512-Byte 80960KA 80960KB TA80960KB ADS-132 80960KA 80960MC LAD26

    80960KB

    Abstract: 80960KB reference
    Text: 80960KB Hardware DesignerÕs Reference Manual Order Number: 270564-002


    Original     		PDF 80960KB 80960KB reference

    micro instruction set of I960 hx

    Abstract: 80960CA 80960CF 80960HA 80960HD 80960HT 80960JA Intel i960
    Text: Intel i960® Processors i960® Architecture Family Product Highlights • 32-bit register-based RISC core in all processors ■ Code compatibility across entire product line ■ Broad selection of price and performance levels ■ Ideal for networking and imaging


    Original     		PDF 32-bit JT-100 USA/1001/500/IL11444 micro instruction set of I960 hx 80960CA 80960CF 80960HA 80960HD 80960HT 80960JA Intel i960

    80960KA

    Abstract: 80960KB 80960MC 270775
    Text: 80960KA EMBEDDED 32-BIT MICROPROCESSOR • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached Instructions


    Original     		PDF 80960KA 32-BIT 512-Byte 132-Lead 80960KA 80960KB 80960MC 270775

    I487

    Abstract: a23 837-1 80960CA 82586 10BASE2 10BASE5 80960KB 82596CA multi 9 c6 dpn
    Text: 82596CA HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR Y Performs Complete CSMA CD Medium Access Control MAC Functions Independently of CPU IEEE 802 3 (EOC) Frame Delimiting Y Y Y Y Supports Industry Standard LANs IEEE TYPE 10BASE-T IEEE TYPE 10BASE5 (Ethernet )


    Original     		PDF 82596CA 32-BIT 10BASE-T 10BASE5 10BASE2 10BASE-F 80960CA 82596CA I487 a23 837-1 82586 10BASE2 10BASE5 80960KB multi 9 c6 dpn

    IN1016

    Abstract: 80960HA 80960HD 80960HT 80960JA 80960JD 80960JF 80960JT PQFP 128 Fast Ethernet Risc
    Text: i960 JA/JF/JD/JT Microprocessors PRODUCT HIGHLIGHTS • Low Power Modes ■ Improved cache design ■ State of the art testability ® ■ i960 processor compatible RISC core ■ 100 MIPS execution for the JT-100 ■ 16-Kbyte 2-way set associative instruction


    Original     		PDF JT-100 16-Kbyte 32-bit JT-100 /0398/5K/IL0316 IN1016 80960HA 80960HD 80960HT 80960JA 80960JD 80960JF 80960JT PQFP 128 Fast Ethernet Risc

    cc196

    Abstract: A-31 IEEE-695 ctools960 i960KB 80960KB Programmer Reference manual i960HA ASM96
    Text:  i960 Processor Software Utilities User’s Guide Order Number: 485277-005 Revision Revision History Date -001 Original Issue. 12/92 -002 Minor corrections. 09/93 -003 Revised for CTOOLS960 R4.5 and GNU/960 R2.4. 05/94 -004 Revised for R5.0. 02/96 -005


    Original     		PDF CTOOLS960 GNU/960 cc196 A-31 IEEE-695 i960KB 80960KB Programmer Reference manual i960HA ASM96

    80960CF

    Abstract: 80960JA 80960CA 80960HA 80960HT 80960JD 80960JF 80960KA 80960SA 80960SB
    Text: SOFTWARE DEVELOPMENT TOOLS CYGNUS Cygnus Developers Kit for the i960 Processor Family • ■ ■ ■ ■ ■ ■ ■ ■ ■ ANSI Conformant GNU C CompilerGCC GNU C+ Compiler - G+ Windowing, Source Level GNU Debugger - GDB Graphical User Interface for GDB


    Original     		PDF RS/6000 80960CF 80960JA 80960CA 80960HA 80960HT 80960JD 80960JF 80960KA 80960SA 80960SB

    80960CA

    Abstract: 80960CF 80960HA 80960HD 80960JA 80960JD 80960JF 80960KA 80960KB 80960SA
    Text: i960 MICROPROCESSOR BENCHMARK REPORT Order Number: 272950-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in


    Original     		PDF sustainin12 20Mhz 25Mhz 33Mhz 40Mhz 25/50Mhz 80960CA 80960CF 80960HA 80960HD 80960JA 80960JD 80960JF 80960KA 80960KB 80960SA

    a4490

    Abstract: 80960MC A80960MC25 i960 mc errata 80960KA 80960KB M8259A intel packaging handbook 240800
    Text: 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Commercial • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ On-Chip Floating Point Unit


    Original     		PDF 80960MC 32-BIT 80-Bit 512-Byte LAD31_ A4492-01 A80960MC. a4490 80960MC A80960MC25 i960 mc errata 80960KA 80960KB M8259A intel packaging handbook 240800

    sun hold RAS 0610

    Abstract: eeprom programmer schematic 24c08 80960KB Programmer Reference manual 270929 KDS crystal 20.000 zilog 4202 IC 24c08 PCI cyclone 3 schematics KDS 4.000 Crystal cpu 80960kx
    Text: i960 Microprocessor User’s Guide for Cyclone and PCI-SDK Evaluation Platforms April 1996 Order Number: 272577-002 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual


    Original     		PDF Z8536 sun hold RAS 0610 eeprom programmer schematic 24c08 80960KB Programmer Reference manual 270929 KDS crystal 20.000 zilog 4202 IC 24c08 PCI cyclone 3 schematics KDS 4.000 Crystal cpu 80960kx

    transistor manual substitution FREE DOWNLOAD

    Abstract: transistor manual substitution gcu 101 setting manual ALL TYPE IC DATA AND manual substitution BOOK Transistor Substitution Data Book 1993 i960 KA/KB Reference Manual 80960KB Programmer Reference manual BP 43 substitution i960 KA/KB Programmers Reference Manual GCC960
    Text: i960 Processor Compiler User’s Manual Order Number: 651230-004 Revision Revision History Date 001 Initial Release 02/96 002 Revised for release 5.1 01/97 003 Revised for release 6.0 12/97 004 Revised for release 6.5 12/98 In the United States, additional copies of this manual or other Intel literature may be obtained by writing:


    Original     		PDF gcc960 transistor manual substitution FREE DOWNLOAD transistor manual substitution gcu 101 setting manual ALL TYPE IC DATA AND manual substitution BOOK Transistor Substitution Data Book 1993 i960 KA/KB Reference Manual 80960KB Programmer Reference manual BP 43 substitution i960 KA/KB Programmers Reference Manual

    ta80960kb

    Abstract: LADI 12V VAX-11
    Text: 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING POINT UNIT • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped


    OCR Scan     		PDF 80960KB 32-BIT 512-Byte 80960KA ta80960kb LADI 12V VAX-11

    VAX-11

    Abstract: MIPS embedded RRU 32
    Text: intj 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped


    OCR Scan     		PDF 80960KB 32-BIT 132-Lead 80-Bit 512-Byte VAX-11 MIPS embedded RRU 32

    Untitled

    Abstract: No abstract text available
    Text: 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING POINT UNIT • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ Built-In Interrupt Controller — 31 Priority Levels, 256 Vectors


    OCR Scan     		PDF 80960KB 32-BIT 512-Byte 132-Lead 80960KB 4fl2bl75

    TA80960KB

    Abstract: 2T818 tl741
    Text: intJ 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped


    OCR Scan     		PDF 80960KB 32-BIT 132-Lead 80-Bit 512-Byte TA80960KB 2T818 tl741

    Untitled

    Abstract: No abstract text available
    Text: 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING POINT UNIT High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz Built-In Interrupt Controller — 31 Priority Levels, 256 Vectors


    OCR Scan     		PDF 80960KB 32-BIT 512-Byte 132-Lead 80960KB 4fl2bl75 01bb514

    LA07

    Abstract: No abstract text available
    Text: 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING POINT UNIT • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped


    OCR Scan     		PDF 80960KB 32-BIT 512-Byte 32-Blt 80960KA LA07

    Untitled

    Abstract: No abstract text available
    Text: ¡n tg l. 82596CA HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR • Performs Complete CSMA/CD Medium Access Control MAC Functions— Independently of CPU — IEEE 802.3 (EOC) Frame Delimiting — HDLC Frame Delimiting ■ Supports Industry Standard LANs


    OCR Scan     		PDF 82596CA 32-BIT 10BASE-T, 10BASE5 10BASE2 10BASE-F 82596CA

    D15105

    Abstract: 44fl5 271060 754for
    Text: in te i 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Military High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS1 Sustained Execution at 25 MHz On-Chip Memory Management Unit


    OCR Scan     		PDF 80960MC 32-BIT M8259A 16-Bytes MIL-STD-883: 80960MC D15105 44fl5 271060 754for

    Intel 486 DX

    Abstract: 486TMsX 82599
    Text: 82596CA HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR • Perform s Com plete C S M A /C D Medium A ccess Control MAC Functions— Independently of CPU — IEEE 802.3 (EOC) Fram e Delimiting ■ Supports Industry Standard LANs — IEEE TYPE 10BASE-T,


    OCR Scan     		PDF 82596CA 32-BIT 10BASE-T, 10BASE5 10BASE2 10BASE-F Intel 486 DX 486TMsX 82599