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    8KX1 Price and Stock

    Aker Technology Company Ltd S1633030-32.768K-X-15-R

    XO 32.768 KHZ CMOS SMD
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    DigiKey S1633030-32.768K-X-15-R Cut Tape 1,000 1
    • 1 $2.36
    • 10 $2.033
    • 100 $1.7551
    • 1000 $1.58468
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    S1633030-32.768K-X-15-R Digi-Reel 1,000 1
    • 1 $2.36
    • 10 $2.033
    • 100 $1.7551
    • 1000 $1.58468
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    S1633030-32.768K-X-15-R Reel 1,000 1,000
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    t-Global Technology TG-A38KX-190-140-1.0-1A

    THERM PAD 190MMX140MM BLUE
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    DigiKey TG-A38KX-190-140-1.0-1A Bulk 34 1
    • 1 $17.64
    • 10 $15.65
    • 100 $13.8821
    • 1000 $12.76242
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    t-Global Technology TG-A38KX-190-140-2.0-2A

    THERM PAD 190MMX140MM BLUE
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    DigiKey TG-A38KX-190-140-2.0-2A Bulk 10 1
    • 1 $28.59
    • 10 $25.369
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    t-Global Technology TG-A38KX-190-140-4.0-2A

    THERM PAD 190MMX140MM BLUE
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    DigiKey TG-A38KX-190-140-4.0-2A Bulk 5 1
    • 1 $49.87
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    t-Global Technology TG-A38KX-190-140-0.5-1A

    THERM PAD 190MMX140MM BLUE
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    DigiKey TG-A38KX-190-140-0.5-1A Bulk 4 1
    • 1 $14.03
    • 10 $12.449
    • 100 $11.0433
    • 1000 $9.79129
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    8KX1 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    memoire

    Abstract: RAM EDAC SEU 350Krad
    Text: 0.6µm CMOS TECHNOLOGY WITH RADIATION TOLERANT FEATURES APPLICATION TO 8Kx16 DUAL PORT RAM and SEA of GATES TECHNOLOGIE CMOS 0.6µm TOLERANTE AUX RADIATIONS APPLICATION A LA MEMOIRE DOUBLE ACCES 8Kx16 ET AUX MERS DE PORTES by Thierry CORBIERE, Valerie LASSERE, Bruno THOMAS, Saïd HACHAD 1


    Original     		PDF 8Kx16 memoire RAM EDAC SEU 350Krad

    krad

    Abstract: 67025E TM1019 RAM SEU
    Text: DPR SCMOS2 Technology Dual Port RAM 8K16 Tolerance to Radiation Abstract This paper proposes a review of the data gathered during radiation testing for the 8Kx16 dual port RAM manufactured using the Radiation Tolerant version of the 0.6µm SCMOS2/2 technology. Both Upset sensitivity


    Original     		PDF 8Kx16 50Krad 10Krad 35Krad NT94055, 9849/92/NL, krad 67025E TM1019 RAM SEU

    Untitled

    Abstract: No abstract text available
    Text: ENERGY METER: Embedded DSP AFE Embedded dspConverters AD73560 AD73560 8/9/01 40 80 2:11 PM AD73360 AD73360 ADSP2185L ADSP2185L 52 52 19 19 16.7 to 26 16.7 to 26 8Kx24 16Kx24 Ed Grokulsky 8Kx16 16Kx16 Rev-4 12/03/00 YES YES YES YES YES YES A A 119 BGA 119 BGA


    Original     		PDF AD73560 AD73360 ADSP2185L 8Kx24 16Kx24 8Kx16 16Kx16

    em78p803

    Abstract: em78p EM78801 ICE803 SEG23
    Text: ELAN MICROELECTRONICS CORP. EM78P803, EM78801, EM78805C difference: ICE803 for 805C mode ICE803 for 803 mode EM78P803 for 805c mode EM78P803 for 803 mode EM78801 EM78805C IC type Romless Romless OTP OTP Mask Mask Program ROM 12kx13 16kx13 8kx13 8kx13 8kx13


    Original     		PDF EM78P803, EM78801, EM78805C ICE803 EM78P803 EM78801 EM78805C 12kx13 em78p EM78801 SEG23

    DSP56116

    Abstract: DSP56166 8Kx16 XC56166FE fully differential opamp
    Text: MOTOROLA DSP Division DSP56166 - Rev. E17T XC56166FE E17T Silicon Enhancement Issue date: April 28th 1994 This information constitutes manual errata The following enhancements have been made from the E52N silicon to the E17T silicon: 1- Increased PROM size from 8Kx16 to 12Kx16


    Original     		PDF DSP56166 XC56166FE 8Kx16 12Kx16 DSP56116 fully differential opamp

    TAG10_

    Abstract: tag12 TAG13 8kx16bit
    Text: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8K x 16 Configuration – 14 Common I/O TAG Bits – 2 Separate I/O Status Bits (VLD and DTY) • Optimized for 256KB cache and 4GB cacheable space


    Original     		PDF 8Kx16-BIT) IDT71V218 256KB 10/12/15ns 48-pin IDT71V218 200mV 71V218 SO48-1) TAG10_ tag12 TAG13 8kx16bit

    TAG12

    Abstract: TAG10_ tag13 8kx16bit cache tag Static RAM
    Text: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8K x 16 Configuration – 14 Common I/O TAG Bits – 2 Separate I/O Status Bits (VLD and DTY) • Optimized for 256KB cache and 4GB cacheable space


    Original     		PDF 8Kx16-BIT) IDT71V218 256KB 10/12/15ns 48-pin IDT71V218 200mV 71V218 SO48-1) TAG12 TAG10_ tag13 8kx16bit cache tag Static RAM

    Untitled

    Abstract: No abstract text available
    Text: TM59PA80 8 Bit Microcontroller FEATURES 1. Memory ‧ 212-byte general purpose register include LCD-Buffer RAM ‧ 8Kx14 internal program memory (OTP ROM) 2. Oscillation Sources ‧ Crystal, Ceramic, Ext RC, SUB Clock ‧ CPU clock divider (1/2, 1/8, 1/16, 1/32)


    Original     		PDF TM59PA80 212-byte 8Kx14 44QFP) 42SDIP) 16-bit 44-QFP 44-QFP 42-SDIP

    8Kx16

    Abstract: TM1019
    Text: Evaluation Report SCMOS2 Radiation Tolerant Technology Dual Port RAM 8Kx16 Tolerance to Radiation by Thierry CORBIERE 1 Work partially funded by French Space Agency [1] Abstract This paper proposes a review of the data gathered during radiation testing for the 8Kx16 dual port


    Original     		PDF 8Kx16 NT94055, 9849/92/NL, TM1019

    8kx16bit ram

    Abstract: 8kx16bit trz a7
    Text: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8K x 16 Configuration – 14 Common I/O TAG Bits – 2 Separate I/O Status Bits (VLD and DTY) • Optimized for 256KB cache and 4GB cacheable space


    Original     		PDF 8Kx16-BIT) IDT71V218 256KB 10/12/15ns 48-pin IDT71V218 200mV 71V218 SO48-1) 8kx16bit ram 8kx16bit trz a7

    LT 543 IC pin diagram

    Abstract: pin diagram of lt 542
    Text: MT56C0818 8K x 18, DUAL 4K x 18 CACHE DATA SRAM |U |C R O N CACHE DATA SRAM SINGLE 8Kx18 SRAM, DUAL 4K x 18 SRAM CONFIGURABLE CACHE DATA SRAM FEATURES PIN ASSIGNMENT Top View • Operates as two 4K x 18 SRAM s w ith common addresses and data; also configurable as a single


    OCR Scan     		PDF MT56C0818 8Kx18 52-Pin LT 543 IC pin diagram pin diagram of lt 542

    block diagram of 486

    Abstract: No abstract text available
    Text: QS88181 Q High-Speed CMOS 8Kx18 Burst Mode SRAM . « i l a , with Address Counter QS88181 ,I w bdM ,!;Aî TÏ,I OoIN Nf Fo OaR FEATURES/BENEFITS • • • • 8Kx18with burst mode for secondary cache 1 clock initial access + 1 clock/word 40, 33, 25 MHz clock frequency


    OCR Scan     		PDF QS88181 8Kx18 8Kx18with 52-pin 52pin AO-12 D8-15 block diagram of 486

    Untitled

    Abstract: No abstract text available
    Text: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors :JÖi'Np Jdt) PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8K x 16 Configuration - 14 Common I/O TAG Bits - 2 Separate I/O Status Bits (VLD and DTY) • Optimized for 256KB cache and 4GB cacheable space


    OCR Scan     		PDF 8Kx16-BIT) IDT71V218 256KB 48-pin 8Kx16 200mV 71V218

    8kx1 RAM

    Abstract: 125 va pt dty 8kx1
    Text: 3.3V 12 8K 8Kx1 6-BIT CACHE-TAG SRAM For 3.3V P r o c e s s o r s FEATURES: H IG H M A T C H o u tp u t is g e n e ra te d w h e n th e s e tw o g ro u p s of d a ta a re th e s a m e fo r a g iven a d d re ss. T h is h ig h -sp e e d M A T C H sig n a l is a v a ila b le as soon a s 10 n s a fte r the a d d re ss


    OCR Scan     		PDF IDT71 200mV 8kx1 RAM 125 va pt dty 8kx1

    Untitled

    Abstract: No abstract text available
    Text: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8 K x 16 C onfiguration - 14 Com m on I/O TAG Bits - 2 Separate I/O Status Bits (VLD and DTY) • O ptim ized for 256KB cache and 4G B cacheable space


    OCR Scan     		PDF 8Kx16-BIT) IDT71V218 256KB 48-pin IDT71V2NOT ro-we-2070

    8kx16bit ram

    Abstract: No abstract text available
    Text: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8 K x 16 C onfiguration - 14 Com m on I/O TAG Bits - 2 Separate I/O Status Bits (VLD and DTY) • O ptim ized for 256KB cache and 4G B cacheable space


    OCR Scan     		PDF 3V128K 8Kx16-BIT) IDT71V218 256KB -10/12/15ns 48-pin MO-118, /15/W 727-fUÂ 8kx16bit ram

    Untitled

    Abstract: No abstract text available
    Text: M IC R O N * MT56C2818 8 K x 18, DUAL 4 K x 18 CACHE DATA SRAM CACHE DATA SRAM SINGLE 8Kx18 SRAM, DUAL 4KX18SRAM CONFIGURABLE CACHE DATA SRAM FEATURES PIN ASSIGNMENT Top View • A u tom atic W RITE cycle com pletion • O p erates a s tw o 4K x 18 SR A M s w ith com m on


    OCR Scan     		PDF MT56C2818 8Kx18 4KX18SRAM

    Untitled

    Abstract: No abstract text available
    Text: MT56C3818 8K x 18, DUAL 4K x 18 CACHE DATA SRAM M IC R O N CACHE DATA SRAM SINGLE 8Kx18 SRAM, DUAL 4KX18SRAM CONFIGURABLE CACHE DATA SRAM FEATURES • Operates as two 4K x 18 SRAMs with common addresses and data; also configurable as a single 8K x 18 SRAM


    OCR Scan     		PDF MT56C3818 8Kx18 4KX18SRAM A0-A12) 52-Pin

    block diagram of 486

    Abstract: sram with address counter
    Text: QS88181 Q High-Speed CMOS_ o _ r _ _ _ _ _ _ 8Kx18 Burst Mode SRAM with Address Counter QS88181 « n \/A M rc ADVANCE INFORMATION FEATURES/BENEFITS • • • • 8Kx18with burst mode for secondarycache 1 clock initial access +1 clock/word 40, 33, 25 MHz clock frequency


    OCR Scan     		PDF QS88181 8Kx18 8Kx18with 52-pin 52pin AO-12 D8-15 block diagram of 486 sram with address counter

    SE012

    Abstract: 00000000ED SE012 diagram EM- 546
    Text: UM5238 4-Bit Microcontroller with 32 Sec. Voice Synthesizer, LCD Driver and PSG Preliminary Features • ■ ■ ■ ■ m ■ ■ ■ ■ ■ ■ ■ 4-bit parallel processing ALU com patible w ith UM6610 8Kx16 bits program ROM bank switchable 128x 4 bits data RAM


    OCR Scan     		PDF UM5238 UM6610 8Kx16 768KHz 122ns SEG13 SEG12 SE012 00000000ED SE012 diagram EM- 546

    S6H2

    Abstract: No abstract text available
    Text: IDT 7MB6042 8KX112 Integrated Device Technology, Inc. WRITABLE CONTROL STORE STATIC RAM MODULE FEATURES: • 8K x 112 high-perform ance W ritable Control Store WCS • Serial Protocol Channel (SPC )-reading, writing and interrogation • High fanout pipeline register


    OCR Scan     		PDF 8KX112 7MB6042 112-bit IDT49FCT818 12-bit IDT49FCT818. S6H2

    Untitled

    Abstract: No abstract text available
    Text: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8K x 16 Configuration - 14 Com m on I/O TA G Bits - 2 S eparate I/O Status Bits (VLD and D TY) • Optim ized for 256K B cache and 4G B cacheable space


    OCR Scan     		PDF 8Kx16-BIT) IDT71V218 48-pin IDT71V21B 8Kx16 4A25771

    Untitled

    Abstract: No abstract text available
    Text: KM 71 8V787 1 2 8 K x 1 8 S y n c h r o n o u s SR A M Document Title 1 2 8Kx1 8-Bi t S y n c h r o n o u s B u r s t S R A M , 3. 3V P o w e r D a t a s h e e t s for 1 0 0 T Q F P Revision History Rev. No. H Istorv Draft Date R e m ar k Rev. 0.0 Initial draft


    OCR Scan     		PDF 8V787 1997x 128Kx18 100-TQFP-1420A

    sram with address counter

    Abstract: RISC and CISC COUNTER LOAD
    Text: QS88181 Q High-Speed CMOS_ _ w _ r _ 8Kx18 Burst Mode SRAM with Address Counter Q S88181 a ni/ ADVANCE IN FO R M A TIO N F E A T U R E S /B E N E F IT S • • • • 8Kx18with burst mode for secondary cache 1 clock initial access +1 clock/word 40, 33, 25 MHz clock frequency


    OCR Scan     		PDF QS88181 8Kx18 QS88181 8Kx18with 52-pin AO-12 D8-15 sram with address counter RISC and CISC COUNTER LOAD