Untitled
Abstract: No abstract text available
Text: SN54LV08, SN74LV08 QUADRUPLE 2ĆINPUT POSITIVEĆAND GATES SCLS186C − FEBRUARY 1993 − REVISED APRIL 1996 SN54LV08 . . . J OR W PACKAGE SN74LV08 . . . D, DB, OR PW PACKAGE TOP VIEW D EPIC (Enhanced-Performance Implanted D D D D 1A 1B 1Y 2A 2B 2Y GND
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SN54LV08,
SN74LV08
SCLS186C
SN54LV08
MIL-STD-883C,
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LV08
Abstract: SN74LV08 SN74LV08D SN74LV08DBLE SN74LV08DR SN74LV08PWLE SN54LV08
Text: SN54LV08, SN74LV08 QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS186C – FEBRUARY 1993 – REVISED APRIL 1996 D D D D D EPIC Enhanced-Performance Implanted CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)
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Original
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SN54LV08,
SN74LV08
SCLS186C
MIL-STD-883C,
JESD-17
300-mil
SN54LV08
LV08
SN74LV08
SN74LV08D
SN74LV08DBLE
SN74LV08DR
SN74LV08PWLE
SN54LV08
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LV08
Abstract: SN54LV08 SN74LV08 SN74LV08D SN74LV08DBLE SN74LV08DR SN74LV08PWLE
Text: SN54LV08, SN74LV08 QUADRUPLE 2ĆINPUT POSITIVEĆAND GATES SCLS186C − FEBRUARY 1993 − REVISED APRIL 1996 D EPIC Enhanced-Performance Implanted D D D D CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)
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Original
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SN54LV08,
SN74LV08
SCLS186C
MIL-STD-883C,
JESD-17
300-mil
LV08
SN54LV08
SN74LV08
SN74LV08D
SN74LV08DBLE
SN74LV08DR
SN74LV08PWLE
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PDF
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LV08
Abstract: SN54LV08 SN74LV08
Text: SN54LV08, SN74LV08 QUADRUPLE 2ĆINPUT POSITIVEĆAND GATES SCLS186C − FEBRUARY 1993 − REVISED APRIL 1996 D EPIC Enhanced-Performance Implanted D D D D CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)
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Original
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SN54LV08,
SN74LV08
SCLS186C
MIL-STD-883C,
JESD-17
300-mil
LV08
SN54LV08
SN74LV08
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PDF
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LV08
Abstract: SN54LV08 SN74LV08
Text: SN54LV08, SN74LV08 QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS186C – FEBRUARY 1993 – REVISED APRIL 1996 D D D D D EPIC Enhanced-Performance Implanted CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)
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Original
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SN54LV08,
SN74LV08
SCLS186C
MIL-STD-883C,
JESD-17
300-mil
SN54LV08
LV08
SN54LV08
SN74LV08
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PDF
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LV08
Abstract: SN54LV08 SN74LV08
Text: SN54LV08, SN74LV08 QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS186C – FEBRUARY 1993 – REVISED APRIL 1996 D D D D D EPIC Enhanced-Performance Implanted CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)
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Original
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SN54LV08,
SN74LV08
SCLS186C
MIL-STD-883C,
JESD-17
300-mil
SN54LV08
LV08
SN54LV08
SN74LV08
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SN74ALVCH162245
Abstract: Schottky Barrier Diode Bus-Termination Array SN7400 CLOCKED SLLS210 SCAD001D TEXAS INSTRUMENTS SN7400 SERIES buffer SN74LVCC4245 sn74154 SDAD001C SN7497
Text: Section 4 Logic Selection Guide ABT – Advanced BiCMOS Technology . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3 ABTE/ETL – Advanced BiCMOS Technology/ Enhanced Transceiver Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9
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SN74HC02 Spice model
Abstract: philips semiconductor data handbook SDAD001C SDFD001B SCAD001D SN7497 spice model SN74AHC14 spice Transistor Crossreference SLLS210 ci ttl sn74ls00
Text: LOGIC OVERVIEW 1 FUNCTIONAL INDEX 2 FUNCTIONAL CROSSĆREFERENCE 3 DEVICE SELECTION GUIDE 4 3 LOGIC SELECTION GUIDE FIRST QUARTER 1997 IMPORTANT NOTICE Texas Instruments TI reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest
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SN74LV08
Abstract: No abstract text available
Text: SN74LV08 QUADRUPLE 2-INPUT POSITIVE-AND GATE _ SCLS186 - FEBRUARY 1993 - REVISED MARCH 1994 • EPIC Enhanced-Performance Implanted CMOS 2-n Process d, d b , o r pw p a c ka g e ( t o p v ie w ) • Typical Vo l p (Output Ground Bounce)
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OCR Scan
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SN74LV08
SCLS186
MIL-STD-883C,
JESD-17
SCLS166
SN74LV08
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Untitled
Abstract: No abstract text available
Text: SN54LVU04, SN74LVU04 HEX INVERTERS S C L S 1 B 5 B - FEBRUARY 1993 - REVISED APRIL 1996 EPIC Enhanced-Performance Implanted CMOS 2-n Process Typical V q l p (Output Ground Bounce) < 0.8 V at V c c . Ta = 25°C Typical V q h v (Output V q h Undershoot)
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OCR Scan
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SN54LVU04,
SN74LVU04
MIL-STD-883C,
JESD-17
300-mil
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SN74LV08
Abstract: No abstract text available
Text: SN74LV08 QUADRUPLE 2-INPUT POSITIVE-AND GATE S C L S 1 86 A - FEBR UARY 1993 - REVISED JULY 1995 1 EPIC Enhanced-Performance Implanted CMOS 2-ji Process D, DB, OR PW PACKAGE CTOP VIEW) Typical V q l p (Output Ground Bounce) < 0.8 V at Vc c = 3.3 V, TA = 25°C
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OCR Scan
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SN74LV08
SCLS186A-FEBRUARY
1993-REVISED
MIL-STD-883C,
JESD-17
8S5303
SN74LV08
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LS186C
Abstract: LS186
Text: SN54LV08, SN74LV08 QUADRUPLE 2-INPUT POSITIVE-AND GATES S C LS 186C - FEBRUARY 1 9 9 3 - REVISED APRIL 1996 EPIC Enhanced-Performance Implanted CMOS 2-ii Process SN54LV08 . . . J OR W PACKAGE SN74LV08 . . . D, DB, OR PW PACKAGE (TOP VIEW) Typical V q l p (Output Ground Bounce)
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OCR Scan
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SN54LV08,
SN74LV08
MIL-STD-883C,
JESD-17
300-mil
SN54LV08
SN74LV08
LS186C
LS186
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LV08
Abstract: No abstract text available
Text: SN54LV08, SN74LV08 QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS1B6C - FEBRUARY 1993 - REVISED APRIL 1996 EPIC Enhanced-Performance Implanted CMOS 2-pi Process SN54LV08 . . . J OR W PACKAGE SN74LV08 . . . D, DB, OR PW PACKAGE (TOP VIEW) Typical V q lp (Output Ground Bounce)
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OCR Scan
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SN54LV08,
SN74LV08
MIL-STD-883C,
JESD-17
300-mil
LV08
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PDF
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