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    SN74LV08 Search Results

    SN74LV08 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    SN74LV08ADR Texas Instruments Quadruple 2-Input Positive-AND Gates 14-SOIC -40 to 125 Visit Texas Instruments Buy
    SN74LV08APWR Texas Instruments Quadruple 2-Input Positive-AND Gates 14-TSSOP -40 to 125 Visit Texas Instruments Buy
    SN74LV08ATPWREP Texas Instruments Enhanced Product Quadruple 2-Input Positive-And Gates 14-TSSOP -40 to 105 Visit Texas Instruments Buy
    SN74LV08APWRE4 Texas Instruments Quadruple 2-Input Positive-AND Gates 14-TSSOP -40 to 125 Visit Texas Instruments Buy
    SN74LV08ARGYR Texas Instruments Quadruple 2-Input Positive-AND Gates 14-VQFN -40 to 125 Visit Texas Instruments Buy
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    SN74LV08 Price and Stock

    Texas Instruments SN74LV08ADGVR

    IC GATE AND 4CH 2-INP 14TVSOP
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    Texas Instruments SN74LV08APWR

    IC GATE AND 4CH 2-INP 14TSSOP
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    Texas Instruments SN74LV08ARGYR

    IC GATE AND 4CH 2-INP 14VQFN
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    Rochester Electronics SN74LV08ARGYR 36,870 1
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    Texas Instruments SN74LV08ADBR

    IC GATE AND 4CH 2-INP 14SSOP
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    Texas Instruments SN74LV08ATPWRG4Q1

    IC GATE AND 4CH 2-INP 14TSSOP
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    SN74LV08 Datasheets (121)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    SN74LV08 Texas Instruments QUADRUPLE 2-INPUT POSITIVE-AND GATES Original PDF
    SN74LV08 Texas Instruments QUADRUPLE 2-INPUT POSITIVE-AND GATES Original PDF
    SN74LV08 Texas Instruments QUADRUPLE 2-INPUT POSITIVE-AND GATES Original PDF
    SN74LV08A Texas Instruments QUADRUPLE 2-INPUT POSITIVE-AND GATES Original PDF
    SN74LV08A Texas Instruments Quadruple 2-Input Positive-AND Gates Original PDF
    SN74LV08AD Texas Instruments SN74LV08 - Quadruple 2-Input Positive-AND Gates 14-SOIC -40 to 85 Original PDF
    SN74LV08AD Texas Instruments Quadruple 2-Input Positive-AND Gates 14-SOIC -40 to 85 Original PDF
    SN74LV08AD Texas Instruments QUADRUPLE 2-INPUT POSITIVE-AND GATES Original PDF
    SN74LV08ADB Texas Instruments SN74LV08 - IC LV/LV-A/LVX/H SERIES, QUAD 2-INPUT AND GATE, PDSO14, Gate Original PDF
    SN74LV08ADB Texas Instruments QUADRUPLE 2-INPUT POSITIVE-AND GATES Original PDF
    SN74LV08ADBE4 Texas Instruments SN74LV08 - IC LV/LV-A/LVX/H SERIES, QUAD 2-INPUT AND GATE, PDSO14, Gate Original PDF
    SN74LV08ADBLE Texas Instruments SN74LV08 - Quadruple 2-Input Positive-AND Gates 14-SSOP -40 to 85 Original PDF
    SN74LV08ADBLE Texas Instruments Quadruple 2-Input Positive-AND Gates 14-SSOP -40 to 85 Original PDF
    SN74LV08ADBLE Texas Instruments QUADRUPLE 2-INPUT POSITIVE-AND GATES Original PDF
    SN74LV08ADBR Texas Instruments SN74LV08 - Quadruple 2-Input Positive-AND Gates 14-SSOP -40 to 85 Original PDF
    SN74LV08ADBR Texas Instruments QUADRUPLE 2-INPUT POSITIVE-AND GATES Original PDF
    SN74LV08ADBR Texas Instruments Quadruple 2-Input Positive-AND Gates 14-SSOP -40 to 85 Original PDF
    SN74LV08ADBRE4 Texas Instruments SN74LV08 - Quadruple 2-Input Positive-AND Gates 14-SSOP -40 to 85 Original PDF
    SN74LV08ADBRE4 Texas Instruments Quadruple 2-Input Positive-AND Gates 14-SSOP -40 to 85 Original PDF
    SN74LV08ADBRE4 Texas Instruments OCTAL BUS TRANSCELVERS WITH 3-STATE OUTPUTS Original PDF
    ...

    SN74LV08 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    Untitled

    Abstract: No abstract text available
    Text: SN74LV08A-EP QUADRUPLE 2-INPUT POSITIVE-AND GATE www.ti.com SCLS481B – MAY 2003 – REVISED JANUARY 2006 FEATURES • • • • • • • • • 1 • Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of


    Original     		SN74LV08A-EP SCLS481B PDF

    LV08A

    Abstract: A115-A C101 SN54LV08A SN74LV08A
    Text: SN54LV08A, SN74LV08A QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS387I – SEPTEMBER 1997 – REVISED JULY 2003 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1Y 2A 2B 2Y 14 1B 1A NC VCC 4B 1 13 4B 2 3 12 4A 4 11 4Y 10 3B 9 3A 5 6 7 8 SN54LV08A . . . FK PACKAGE


    Original     		SN54LV08A, SN74LV08A SCLS387I SN54LV08A LV08A A115-A C101 SN54LV08A SN74LV08A PDF

    Untitled

    Abstract: No abstract text available
    Text: SN74LV08AĆQ1 QUADRUPLE 2ĆINPUT POSITIVEĆAND GATE SCLS465B − FEBRUARY 2003 − REVISED MAY 2004 D Qualification in Accordance With PW PACKAGE TOP VIEW AEC-Q100† D Qualified for Automotive Applications D Customer-Specific Configuration Control D D D


    Original     		SN74LV08AQ1 SCLS465B AEC-Q100 000-V A114-A) A115-A) PDF

    Untitled

    Abstract: No abstract text available
    Text: SN54LV08A, SN74LV08A QUADRUPLE 2ĆINPUT POSITIVEĆAND GATES SCLS387K − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y


    Original     		SN54LV08A, SN74LV08A SCLS387K 000-V A114-A) A115-A) SN54LV08A SN74LV08A PDF

    LV08A

    Abstract: No abstract text available
    Text: SN74LV08AĆQ1 QUADRUPLE 2ĆINPUT POSITIVEĆAND GATE SCLS465B − FEBRUARY 2003 − REVISED MAY 2004 D Qualification in Accordance With PW PACKAGE TOP VIEW AEC-Q100† D Qualified for Automotive Applications D Customer-Specific Configuration Control D D D


    Original     		SN74LV08AQ1 SCLS465B AEC-Q100 000-V A114-A) A115-A) LV08A PDF

    A115-A

    Abstract: C101 LV08A SN54LV08A SN74LV08A
    Text: SN54LV08A, SN74LV08A QUADRUPLE 2ĆINPUT POSITIVEĆAND GATES SCLS387K − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y


    Original     		SN54LV08A, SN74LV08A SCLS387K SN54LV08A SN74LAmplifiers A115-A C101 LV08A SN54LV08A SN74LV08A PDF

    Untitled

    Abstract: No abstract text available
    Text: SN74LV08A-EP QUADRUPLE 2-INPUT POSITIVE-AND GATE www.ti.com SCLS481B – MAY 2003 – REVISED JANUARY 2006 FEATURES • • • • • • • • • 1 • Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of


    Original     		SN74LV08A-EP SCLS481B PDF

    Untitled

    Abstract: No abstract text available
    Text: SN74LV08AĆEP QUADRUPLE 2ĆINPUT POSITIVEĆAND GATE SCLS481A − MAY 2003 − REVISED MAY 2004 D Controlled Baseline D D D D D D D D Ioff Supports Partial-Power-Down Mode − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of


    Original     		SN74LV08AEP SCLS481A 000-V A114-A) A115-A) PDF

    LV08A

    Abstract: 74LV08A
    Text: SN54LV08A, SN74LV08A QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS387F – SEPTEMBER 1997 – REVISED AUGUST 2002 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1Y 2A 2B 2Y 14 1B 1A NC VCC 4B 1 2 13 4B 3 12 4A 4 11 4Y GND 10 3B 9 3A 5 6 7 8 SN54LV08A . . . FK PACKAGE


    Original     		SN54LV08A, SN74LV08A SCLS387F 000-V A114-A) A115-A) SN54LV08A LV08A 74LV08A PDF

    LV08A

    Abstract: 74LV08A A115-A C101 SN54LV08A SN74LV08A
    Text: SN54LV08A, SN74LV08A QUADRUPLE 2ĆINPUT POSITIVEĆAND GATES SCLS387K − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y


    Original     		SN54LV08A, SN74LV08A SCLS387K SN54LV08A SN74L LV08A 74LV08A A115-A C101 SN54LV08A SN74LV08A PDF

    Untitled

    Abstract: No abstract text available
    Text: SN54LV08A, SN74LV08A QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS387L − SEPTEMBER 1997 − REVISED OCTOBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce D Ioff Supports Partial-Power-Down Mode D D <0.8 V at VCC = 3.3 V, TA = 25°C


    Original     		SN54LV08A, SN74LV08A SCLS387L PDF

    Untitled

    Abstract: No abstract text available
    Text: SN54LV08A, SN74LV08A QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS387L − SEPTEMBER 1997 − REVISED OCTOBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		SN54LV08A, SN74LV08A SCLS387L PDF

    Untitled

    Abstract: No abstract text available
    Text: SN54LV08, SN74LV08 QUADRUPLE 2ĆINPUT POSITIVEĆAND GATES SCLS186C − FEBRUARY 1993 − REVISED APRIL 1996 SN54LV08 . . . J OR W PACKAGE SN74LV08 . . . D, DB, OR PW PACKAGE TOP VIEW D EPIC  (Enhanced-Performance Implanted D D D D 1A 1B 1Y 2A 2B 2Y GND


    Original     		SN54LV08, SN74LV08 SCLS186C SN54LV08 MIL-STD-883C, PDF

    LV08A

    Abstract: A115-A C101 SN54LV08A SN74LV08A SN74LV08ARGYR 74LV08a
    Text: SN54LV08A, SN74LV08A QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS387L − SEPTEMBER 1997 − REVISED OCTOBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce D Ioff Supports Partial-Power-Down Mode D D <0.8 V at VCC = 3.3 V, TA = 25°C


    Original     		SN54LV08A, SN74LV08A SCLS387L LV08A A115-A C101 SN54LV08A SN74LV08A SN74LV08ARGYR 74LV08a PDF

    A115-A

    Abstract: C101 LV08A SN54LV08A SN74LV08A
    Text: SN54LV08A, SN74LV08A QUADRUPLE 2ĆINPUT POSITIVEĆAND GATES SCLS387K − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y


    Original     		SN54LV08A, SN74LV08A SCLS387K SN54LV08A SN74Ltrollers A115-A C101 LV08A SN54LV08A SN74LV08A PDF

    LV08

    Abstract: SN74LV08 SN74LV08D SN74LV08DBLE SN74LV08DR SN74LV08PWLE SN54LV08
    Text: SN54LV08, SN74LV08 QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS186C – FEBRUARY 1993 – REVISED APRIL 1996 D D D D D EPIC  Enhanced-Performance Implanted CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		SN54LV08, SN74LV08 SCLS186C MIL-STD-883C, JESD-17 300-mil SN54LV08 LV08 SN74LV08 SN74LV08D SN74LV08DBLE SN74LV08DR SN74LV08PWLE SN54LV08 PDF

    LV08A

    Abstract: A115-A C101 SN54LV08A SN74LV08A
    Text: SN54LV08A, SN74LV08A QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS387E – SEPTEMBER 1997 – REVISED JANUARY 2001 D D D D SN54LV08A . . . J OR W PACKAGE SN74LV08A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce)


    Original     		SN54LV08A, SN74LV08A SCLS387E SN54LV08A 000-V A114-A) A115-A) LV08A A115-A C101 SN54LV08A SN74LV08A PDF

    LV08A

    Abstract: SN54LV08A SN74LV08A
    Text: SN54LV08A, SN74LV08A QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS387D – SEPTEMBER 1997 – REVISED MAY 2000 D D D D D D D EPIC  Enhanced-Performance Implanted CMOS Process Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		SN54LV08A, SN74LV08A SCLS387D MIL-STD-883, LV08A SN54LV08A SN74LV08A PDF

    Untitled

    Abstract: No abstract text available
    Text: SN74LV08A-Q1 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCLS465C − FEBRUARY 2003 − REVISED JANUARY 2008 D Qualified for Automotive Applications D Typical VOLP Output Ground Bounce D D D D D PW PACKAGE (TOP VIEW) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		SN74LV08A-Q1 SCLS465C 000-V A114-A) A115-A) PDF

    Untitled

    Abstract: No abstract text available
    Text: SN54LV08A, SN74LV08A QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS387L − SEPTEMBER 1997 − REVISED OCTOBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce D Ioff Supports Partial-Power-Down Mode D D <0.8 V at VCC = 3.3 V, TA = 25°C


    Original     		SN54LV08A, SN74LV08A SCLS387L 000-V A114-A) A115-A) PDF

    C101

    Abstract: Q100 SN74LV08A A115-A AEC-Q100
    Text: SN74LV08AĆQ1 QUADRUPLE 2ĆINPUT POSITIVEĆAND GATE SCLS465B − FEBRUARY 2003 − REVISED MAY 2004 D Qualification in Accordance With PW PACKAGE TOP VIEW AEC-Q100† D Qualified for Automotive Applications D Customer-Specific Configuration Control D D D


    Original     		SN74LV08AQ1 SCLS465B AEC-Q100 000-V A114-A) A115-plifiers C101 Q100 SN74LV08A A115-A AEC-Q100 PDF

    SN74LV08

    Abstract: No abstract text available
    Text: SN74LV08 QUADRUPLE 2-INPUT POSITIVE-AND GATE S C L S 1 86 A - FEBR UARY 1993 - REVISED JULY 1995 1 EPIC Enhanced-Performance Implanted CMOS 2-ji Process D, DB, OR PW PACKAGE CTOP VIEW) Typical V q l p (Output Ground Bounce) < 0.8 V at Vc c = 3.3 V, TA = 25°C


    OCR Scan     		SN74LV08 SCLS186A-FEBRUARY 1993-REVISED MIL-STD-883C, JESD-17 8S5303 SN74LV08 PDF

    SN74LV08

    Abstract: No abstract text available
    Text: SN74LV08 QUADRUPLE 2-INPUT POSITIVE-AND GATE _ SCLS186 - FEBRUARY 1993 - REVISED MARCH 1994 • EPIC Enhanced-Performance Implanted CMOS 2-n Process d, d b , o r pw p a c ka g e ( t o p v ie w ) • Typical Vo l p (Output Ground Bounce)


    OCR Scan     		SN74LV08 SCLS186 MIL-STD-883C, JESD-17 SCLS166 SN74LV08 PDF

    LS387

    Abstract: No abstract text available
    Text: SN54LV08A, SN74LV08A QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS387B - SEPTEMBER 1997 - REVISED MAY 1998 EPICM Enhanced-Performance Implanted CMOS Process SN54LV08A . . . J OR W PACKAGE SN74LV08A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW) Typical V q l p (Output Ground Bounce)


    OCR Scan     		SN54LV08A, SN74LV08A SCLS387B JESD17 MIL-STD-883, 300-mil LS387 PDF