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    SN54LV165A Search Results

    SN54LV165A Datasheets (5)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    SN54LV165A Texas Instruments PARALLEL-LOAD 8-BIT SHIFT REGISTERS Original PDF
    SN54LV165A Texas Instruments PARALLEL-LOAD 8-BIT SHIFT REGISTERS Original PDF
    SN54LV165AFK Texas Instruments PARALLEL-LOAD 8-BIT SHIFT REGISTERS Original PDF
    SN54LV165AJ Texas Instruments PARALLEL-LOAD 8-BIT SHIFT REGISTERS Original PDF
    SN54LV165AW Texas Instruments PARALLEL-LOAD 8-BIT SHIFT REGISTERS Original PDF

    SN54LV165A Datasheets Context Search

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    Untitled

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402C – APRIL 1998 – REVISED MAY 2000 D D D D D EPIC  Enhanced-Performance Implanted CMOS Process 2-V to 5.5-V VCC Operation Support Mixed-Mode Voltage Operation on All Ports Latch-Up Performance Exceeds 250 mA Per


    Original     		PDF SN54LV165A, SN74LV165A SCLS402C LV165A CopyrighU001B, SDYU001N, SCET004, SCAU001A, SCEM132,

    Untitled

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402C – APRIL 1998 – REVISED MAY 2000 D D D D D EPIC  Enhanced-Performance Implanted CMOS Process 2-V to 5.5-V VCC Operation Support Mixed-Mode Voltage Operation on All Ports Latch-Up Performance Exceeds 250 mA Per


    Original     		PDF SN54LV165A, SN74LV165A SCLS402C LV165A SZZU001B, SDYU001M, SCAU001A, SN74LV165A, ////roarer/root/data13/imaging/BIT.

    A115-A

    Abstract: C101 LV165A SN54LV165A SN74LV165A SN74LV165APWRG3
    Text: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402M − APRIL 1998 − REVISED DECEMBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A


    Original     		PDF SN54LV165A, SN74LV165A SCLS402M 000-V A114-A) A115-A) SN54LV165A A115-A C101 LV165A SN54LV165A SN74LV165A SN74LV165APWRG3

    Untitled

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402C – APRIL 1998 – REVISED MAY 2000 D D D D D EPIC  Enhanced-Performance Implanted CMOS Process 2-V to 5.5-V VCC Operation Support Mixed-Mode Voltage Operation on All Ports Latch-Up Performance Exceeds 250 mA Per


    Original     		PDF SN54LV165A, SN74LV165A SCLS402C LV165A SN74LV165AD SN74LV165ADBR SN74LV165ADGVR SN74LV165ADR SN74LV165APWR

    LV165A

    Abstract: SN54LV165A SN74LV165A
    Text: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402C – APRIL 1998 – REVISED MAY 2000 D D D D D EPIC  Enhanced-Performance Implanted CMOS Process 2-V to 5.5-V VCC Operation Support Mixed-Mode Voltage Operation on All Ports Latch-Up Performance Exceeds 250 mA Per


    Original     		PDF SN54LV165A, SN74LV165A SCLS402C MIL-STD-883, SN54LV165A LV165A SN54LV165A SN74LV165A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402L − APRIL 1998 − REVISED MAY 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A


    Original     		PDF SN54LV165A, SN74LV165A SCLS402L 000-V A114-A) A115-A) SN54LV165A

    lv165a

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A www.ti.com SCLS402N – APRIL 1998 – REVISED JULY 2013 PARALLEL-LOAD 8-BIT SHIFT REGISTERS Check for Samples: SN54LV165A, SN74LV165A FEATURES DESCRIPTION • • • The ’LV165A devices are parallel-load, 8-bit shift registers designed for 2-V to 5.5-V VCC operation.


    Original     		PDF SN54LV165A, SN74LV165A SCLS402N LV165A 000-V A114-A) A115-A)

    Untitled

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		PDF SN54LV165A, SN74LV165A SCLS402K 000-V A114-A) A115-A) SN54LV165A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		PDF SN54LV165A, SN74LV165A SCLS402K 000-V A114-A) A115-A) SN54LV165A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402M − APRIL 1998 − REVISED DECEMBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A


    Original     		PDF SN54LV165A, SN74LV165A SCLS402M 000-V A114-A) A115-A) SN54LV165A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		PDF SN54LV165A, SN74LV165A SCLS402K 000-V A114-A) A115-A) SN54LV165A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode Operation


    Original     		PDF SN54LV165A, SN74LV165A SCLS402K 000-V A114-A) A115-A) SN54LV165A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402M − APRIL 1998 − REVISED DECEMBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A


    Original     		PDF SN54LV165A, SN74LV165A SCLS402M 000-V A114-A) A115-A) SN54LV165A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402H – APRIL 1998 – REVISED JANUARY 2003 SN54LV165A . . . J OR W PACKAGE SN74LV165A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 3 14 4 13 5 12 6 11 7 10 8 9 VCC CLK INH D C B A SER QH CLK


    Original     		PDF SN54LV165A, SN74LV165A SCLS402H 000-V A114-A) A115-A) SN54LV165A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A www.ti.com SCLS402N – APRIL 1998 – REVISED JULY 2013 PARALLEL-LOAD 8-BIT SHIFT REGISTERS Check for Samples: SN54LV165A, SN74LV165A FEATURES DESCRIPTION • • • The ’LV165A devices are parallel-load, 8-bit shift registers designed for 2-V to 5.5-V VCC operation.


    Original     		PDF SN54LV165A, SN74LV165A SCLS402N 000-V A114-A) A115-A) LV165A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		PDF SN54LV165A, SN74LV165A SCLS402K 000-V A114-A) A115-A) SN54LV165A

    74lv165a

    Abstract: lv165a A115-A C101 SN54LV165A SN74LV165A SN74LV165ARGYR LV165
    Text: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		PDF SN54LV165A, SN74LV165A SCLS402K SN54LV165A 74lv165a lv165a A115-A C101 SN54LV165A SN74LV165A SN74LV165ARGYR LV165

    A115-A

    Abstract: C101 SN54LV165A SN74LV165A SN74LV165ARGYR
    Text: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		PDF SN54LV165A, SN74LV165A SCLS402K SN54LV165A A115-A C101 SN54LV165A SN74LV165A SN74LV165ARGYR

    A115-A

    Abstract: C101 SN54LV165A SN74LV165A SN74LV165ARGYR
    Text: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		PDF SN54LV165A, SN74LV165A SCLS402K SN54LV165A A115-A C101 SN54LV165A SN74LV165A SN74LV165ARGYR

    lv165a

    Abstract: SN54LV165A SN74LV165A SN74LV165ARGYR A115-A C101
    Text: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		PDF SN54LV165A, SN74LV165A SCLS402K SN54LV165A lv165a SN54LV165A SN74LV165A SN74LV165ARGYR A115-A C101

    A115-A

    Abstract: C101 SN54LV165A SN74LV165A SN74LV165ARGYR
    Text: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402I – APRIL 1998 – REVISED JULY 2003 SN54LV165A . . . J OR W PACKAGE SN74LV165A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 3 14 4 13 5 12 6 11 7 10 8 9 VCC CLK INH D C B A SER QH CLK E


    Original     		PDF SN54LV165A, SN74LV165A SCLS402I SN54LV165A A115-A C101 SN54LV165A SN74LV165A SN74LV165ARGYR

    Untitled

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A www.ti.com SCLS402N – APRIL 1998 – REVISED JULY 2013 PARALLEL-LOAD 8-BIT SHIFT REGISTERS Check for Samples: SN54LV165A, SN74LV165A FEATURES DESCRIPTION • • • The ’LV165A devices are parallel-load, 8-bit shift registers designed for 2-V to 5.5-V VCC operation.


    Original     		PDF SN54LV165A, SN74LV165A SCLS402N LV165A 000-V A114-A) A115-A)

    A115-A

    Abstract: C101 LV165A SN54LV165A SN74LV165A
    Text: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402D – APRIL 1998 – REVISED JANUARY 2001 D D D D 2-V to 5.5-V VCC Operation Support Mixed-Mode Voltage Operation on All Ports Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22


    Original     		PDF SN54LV165A, SN74LV165A SCLS402D 000-V A114-A) A115-A) SN54LV165A A115-A C101 LV165A SN54LV165A SN74LV165A

    74LV165A

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402M − APRIL 1998 − REVISED DECEMBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A


    Original     		PDF SN54LV165A, SN74LV165A SCLS402M 000-V A114-A) A115-A) SN54LV165A 74LV165A