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    Untitled

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		PDF SN54LV165A, SN74LV165A SCLS402K 000-V A114-A) A115-A) SN54LV165A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		PDF SN54LV165A, SN74LV165A SCLS402K 000-V A114-A) A115-A) SN54LV165A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		PDF SN54LV165A, SN74LV165A SCLS402K 000-V A114-A) A115-A) SN54LV165A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode Operation


    Original     		PDF SN54LV165A, SN74LV165A SCLS402K 000-V A114-A) A115-A) SN54LV165A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		PDF SN54LV165A, SN74LV165A SCLS402K 000-V A114-A) A115-A) SN54LV165A

    74lv165a

    Abstract: lv165a A115-A C101 SN54LV165A SN74LV165A SN74LV165ARGYR LV165
    Text: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		PDF SN54LV165A, SN74LV165A SCLS402K SN54LV165A 74lv165a lv165a A115-A C101 SN54LV165A SN74LV165A SN74LV165ARGYR LV165

    A115-A

    Abstract: C101 SN54LV165A SN74LV165A SN74LV165ARGYR
    Text: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		PDF SN54LV165A, SN74LV165A SCLS402K SN54LV165A A115-A C101 SN54LV165A SN74LV165A SN74LV165ARGYR

    A115-A

    Abstract: C101 SN54LV165A SN74LV165A SN74LV165ARGYR
    Text: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		PDF SN54LV165A, SN74LV165A SCLS402K SN54LV165A A115-A C101 SN54LV165A SN74LV165A SN74LV165ARGYR

    lv165a

    Abstract: SN54LV165A SN74LV165A SN74LV165ARGYR A115-A C101
    Text: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		PDF SN54LV165A, SN74LV165A SCLS402K SN54LV165A lv165a SN54LV165A SN74LV165A SN74LV165ARGYR A115-A C101

    A115-A

    Abstract: C101 SN54LV165A SN74LV165A SN74LV165ARGYR
    Text: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		PDF SN54LV165A, SN74LV165A SCLS402K SN54LV165A A115-A C101 SN54LV165A SN74LV165A SN74LV165ARGYR

    A115-A

    Abstract: C101 SN54LV165A SN74LV165A SN74LV165ARGYR
    Text: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		PDF SN54LV165A, SN74LV165A SCLS402K SN54LV165A A115-A C101 SN54LV165A SN74LV165A SN74LV165ARGYR

    A115-A

    Abstract: C101 SN54LV165A SN74LV165A SN74LV165ARGYR
    Text: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		PDF SN54LV165A, SN74LV165A SCLS402K SN54LV165A A115-A C101 SN54LV165A SN74LV165A SN74LV165ARGYR

    Untitled

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		PDF SN54LV165A, SN74LV165A SCLS402K 000-V A114-A) A115-A) SN54LV165A SN74LV165A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		PDF SN54LV165A, SN74LV165A SCLS402K 000-V A114-A) A115-A) SN54LV165A