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    SN74LV165APWE4 Search Results

    SN74LV165APWE4 Datasheets (3)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    SN74LV165APWE4 Texas Instruments SN74LV165 - Parallel-Load 8-Bit Shift Registers 16-TSSOP -40 to 125 Original PDF
    SN74LV165APWE4 Texas Instruments Parallel-Load 8-Bit Shift Registers 16-TSSOP -40 to 85 Original PDF
    SN74LV165APWE4 Texas Instruments Parallel-Load 8-Bit Shift Registers Original PDF

    SN74LV165APWE4 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    A115-A

    Abstract: C101 LV165A SN54LV165A SN74LV165A SN74LV165APWRG3
    Text: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402M − APRIL 1998 − REVISED DECEMBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A


    Original     		PDF SN54LV165A, SN74LV165A SCLS402M 000-V A114-A) A115-A) SN54LV165A A115-A C101 LV165A SN54LV165A SN74LV165A SN74LV165APWRG3

    Untitled

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402L − APRIL 1998 − REVISED MAY 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A


    Original     		PDF SN54LV165A, SN74LV165A SCLS402L 000-V A114-A) A115-A) SN54LV165A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		PDF SN54LV165A, SN74LV165A SCLS402K 000-V A114-A) A115-A) SN54LV165A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		PDF SN54LV165A, SN74LV165A SCLS402K 000-V A114-A) A115-A) SN54LV165A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402M − APRIL 1998 − REVISED DECEMBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A


    Original     		PDF SN54LV165A, SN74LV165A SCLS402M 000-V A114-A) A115-A) SN54LV165A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		PDF SN54LV165A, SN74LV165A SCLS402K 000-V A114-A) A115-A) SN54LV165A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode Operation


    Original     		PDF SN54LV165A, SN74LV165A SCLS402K 000-V A114-A) A115-A) SN54LV165A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402M − APRIL 1998 − REVISED DECEMBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A


    Original     		PDF SN54LV165A, SN74LV165A SCLS402M 000-V A114-A) A115-A) SN54LV165A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402M − APRIL 1998 − REVISED DECEMBER 2010 D Latch-Up Performance Exceeds 250 mA Per D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D JESD 17


    Original     		PDF SN54LV165A, SN74LV165A SCLS402M 000-V A114-A) A115-A) SN54LV165A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A www.ti.com SCLS402N – APRIL 1998 – REVISED JULY 2013 PARALLEL-LOAD 8-BIT SHIFT REGISTERS Check for Samples: SN54LV165A, SN74LV165A FEATURES DESCRIPTION • • • The ’LV165A devices are parallel-load, 8-bit shift registers designed for 2-V to 5.5-V VCC operation.


    Original     		PDF SN54LV165A, SN74LV165A SCLS402N 000-V A114-A) A115-A) LV165A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		PDF SN54LV165A, SN74LV165A SCLS402K 000-V A114-A) A115-A) SN54LV165A

    74lv165a

    Abstract: lv165a A115-A C101 SN54LV165A SN74LV165A SN74LV165ARGYR LV165
    Text: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		PDF SN54LV165A, SN74LV165A SCLS402K SN54LV165A 74lv165a lv165a A115-A C101 SN54LV165A SN74LV165A SN74LV165ARGYR LV165

    A115-A

    Abstract: C101 SN54LV165A SN74LV165A SN74LV165ARGYR
    Text: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		PDF SN54LV165A, SN74LV165A SCLS402K SN54LV165A A115-A C101 SN54LV165A SN74LV165A SN74LV165ARGYR

    A115-A

    Abstract: C101 SN54LV165A SN74LV165A SN74LV165ARGYR
    Text: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		PDF SN54LV165A, SN74LV165A SCLS402K SN54LV165A A115-A C101 SN54LV165A SN74LV165A SN74LV165ARGYR

    Untitled

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A www.ti.com SCLS402N – APRIL 1998 – REVISED JULY 2013 PARALLEL-LOAD 8-BIT SHIFT REGISTERS Check for Samples: SN54LV165A, SN74LV165A FEATURES DESCRIPTION • • • The ’LV165A devices are parallel-load, 8-bit shift registers designed for 2-V to 5.5-V VCC operation.


    Original     		PDF SN54LV165A, SN74LV165A SCLS402N LV165A 000-V A114-A) A115-A)

    74LV165A

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402M − APRIL 1998 − REVISED DECEMBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A


    Original     		PDF SN54LV165A, SN74LV165A SCLS402M 000-V A114-A) A115-A) SN54LV165A 74LV165A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402M − APRIL 1998 − REVISED DECEMBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A


    Original     		PDF SN54LV165A, SN74LV165A SCLS402M 000-V A114-A) A115-A) SN54LV165A

    A115-A

    Abstract: C101 SN54LV165A SN74LV165A SN74LV165ARGYR
    Text: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		PDF SN54LV165A, SN74LV165A SCLS402K SN54LV165A A115-A C101 SN54LV165A SN74LV165A SN74LV165ARGYR

    Untitled

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A www.ti.com SCLS402N – APRIL 1998 – REVISED JULY 2013 PARALLEL-LOAD 8-BIT SHIFT REGISTERS Check for Samples: SN54LV165A, SN74LV165A FEATURES DESCRIPTION • • • The ’LV165A devices are parallel-load, 8-bit shift registers designed for 2-V to 5.5-V VCC operation.


    Original     		PDF SN54LV165A, SN74LV165A SCLS402N LV165A 000-V A114-A) A115-A)

    Untitled

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402M − APRIL 1998 − REVISED DECEMBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A


    Original     		PDF SN54LV165A, SN74LV165A SCLS402M 000-V A114-A) A115-A) SN54LV165A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A www.ti.com SCLS402N – APRIL 1998 – REVISED JULY 2013 PARALLEL-LOAD 8-BIT SHIFT REGISTERS Check for Samples: SN54LV165A, SN74LV165A FEATURES DESCRIPTION • • • The ’LV165A devices are parallel-load, 8-bit shift registers designed for 2-V to 5.5-V VCC operation.


    Original     		PDF SN54LV165A, SN74LV165A SCLS402N LV165A 000-V A114-A) A115-A)

    A115-A

    Abstract: C101 SN54LV165A SN74LV165A SN74LV165ARGYR
    Text: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		PDF SN54LV165A, SN74LV165A SCLS402K SN54LV165A A115-A C101 SN54LV165A SN74LV165A SN74LV165ARGYR

    Untitled

    Abstract: No abstract text available
    Text: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402M − APRIL 1998 − REVISED DECEMBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A


    Original     		PDF SN54LV165A, SN74LV165A SCLS402M 000-V A114-A) A115-A) SN54LV165A

    A115-A

    Abstract: C101 SN54LV165A SN74LV165A SN74LV165ARGYR
    Text: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		PDF SN54LV165A, SN74LV165A SCLS402K SN54LV165A A115-A C101 SN54LV165A SN74LV165A SN74LV165ARGYR