STP2014
Abstract: MK48T08-1 EBA11 STP2104 AmZ8 AD27 AD29 AD30
Text: STP2014.frm 1 Mon Jul 7 08:25:34 1997 STP2014 July 1997 SEC DATA SHEET SBus-to-EBus Controller DESCRIPTION The STP2014 SBus-to-EBus Controller SEC is an interface between the SBus and the EBus that is used for slow I/O devices such as TOD, EPROM, serial port, and keyboard/mouse. The STP2014 also houses the interrupt control and steering logic, the timer/counter registers, reset logic, and miscellaneous registers. The
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STP2014
STP2014
STP2104
STP2014PQFP
160-Pin
MK48T08-1
EBA11
AmZ8
AD27
AD29
AD30
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PDF
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STP2016
Abstract: SuperSPARC mbus 10 application STP2011 STP2016QFP mbus MCLK11 MOSC STP2012
Text: STP2016 July 1997 Clock-2 Generator System Clock Generator DATA SHEET DESCRIPTION The STP2016 Clock-2 Chip generates clock signals for components on the SBus and MBus. The MBus and SBus are used by SPARC processors, such as SuperSPARC™. The MBus is designed for multiprocessing MP , operating at
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STP2016
STP2016
64-bit
PQFP100
100-Pin
STP2016QFP
SuperSPARC
mbus 10 application
STP2011
STP2016QFP
mbus
MCLK11
MOSC
STP2012
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PDF
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53C90A
Abstract: ncr53c90 STP2012 53C90 AD12 AM7990 STP2013 EIRQ15 STP2011 53c90 scsi
Text: STP2012QFP July 1997 DMA2 DATA SHEET SBus DMA Controller DESCRIPTION The STP2012 SBus DMA Controller DMA2 provides three channels for DMA transfers over the SBus. It has three external interfaces designed to provide DMA access to one AMD Am7990 Local Area Network Controller for the Ethernet (LANCE), one NCR 53C90 SCSI controller (ESP), and one programmable Centronics-type parallel port. The
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STP2012QFP
STP2012
Am7990
53C90
STP2012PQFP
160-Pin
STP2012
53C90A
ncr53c90
AD12
STP2013
EIRQ15
STP2011
53c90 scsi
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PDF
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mbus master circuit
Abstract: STP2011 MAD44 mbus 10 application three phase ESC circuit diagrams MAD50
Text: STP2011PGA-50 July 1997 MSI DATA SHEET MBus-to-SBus Interface DESCRIPTION The STP2011 MBus-to-SBus Interface MSI provides an interface between the MBus and the SBus and controls access to the I/O subsystem. The MSI consists of two main functional blocks: the Memory Subsystem and the I/O Subsystem.
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STP2011PGA-50
STP2011
STP2011PGA
279-Pin
STP2011
mbus master circuit
MAD44
mbus 10 application
three phase ESC circuit diagrams
MAD50
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PDF
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STP2018TAB
Abstract: STP2018 m-bus
Text: STP2018 July 1997 MSBI MBus to SBus Interface DATA SHEET DESCRIPTION The STP2018 MBus to SBus Interface MSBI provides a bus bridge between two different busses used by a number of SPARC microprocessors and controls access to the I/O subsystem. The MBus is designed for multiprocessing (MP),
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STP2018
STP2018
64-bit
288-Lead
STP2018TAB
STP2018TAB
m-bus
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PDF
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Untitled
Abstract: No abstract text available
Text: STP2014 S un M ic r o e l e c t r o n ic s July 1997 SEC DATA SHEET SBus-to-EBus Controller D e s c r ip t io n The STP2014 SBus-to-EBus Controller SEC is an interface between the SBus and the EBus that is used for slow I/O devices such as TOD, EPROM, serial port, and keyboard/mouse. The STP2014 also houses the inter
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OCR Scan
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STP2014
STP2014
STP2104
STP2014PQFP
160-Pin
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PDF
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STP2014QFP
Abstract: No abstract text available
Text: STP2014.frm 1 Mon Jul 7 08:25:34 1997 S un M e ic r o e l e c t r o n ic s J u ly 1997 SEC DATA SHEET SBus-to-EBus Controller D e s c r ip t io n The STP2014 SBus-to-EBus Controller SEC is an interface between the SBus and the EBus that is used for slow I/O devices such as TOD, EPROM, serial port, and keyboard/m ouse. The STP2014 also houses the inter
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OCR Scan
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STP2014
STP2104
STP2014
TP2014PQ
160-Pin
STP2014QFP
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PDF
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E-BA8
Abstract: ISOS refer STP2104
Text: S un M ic ro electro nics July 1997 SEC DATA SHEET SBus-to-EBus Controller D e s c r ip t io n The STP2014 SBus-to-EBus Controller SEC is an interface between the SBus and the EBus that is used for slow I/O devices such as TOD, EPROM, serial port, and keyboard/mouse. The STP2014 also houses the inter
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OCR Scan
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STP2014
S1T2014
STP2104
STP2014
E-BA8
ISOS refer
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PDF
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lcd cross reference
Abstract: SME2411BGA SuperSPARC 805-0086-02 PMC cross reference STP2003QFP ATM622-S STP3010 STP2014QFP STP2024QFP
Text: S un M icroelectronics July 1997 Data Sheets listed by Product Name Cross Reference List Advanced PCI Bridge SME2411BGA ATM622-S SAR SME4050BGA 802-7894-02 Color LCD Controller STP3031 STP3031 Crossbar Switch XB1 STP2230SOP 802-7955-02 Dual System Controller
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OCR Scan
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ATM622-S
85/110MHz
UltraSPARC-1167
UltraSPARC-11
UltraSPARC-ll/300
Buffer-50
STP1030A
STP5111A-200
STP5110A-167
lcd cross reference
SME2411BGA
SuperSPARC
805-0086-02
PMC cross reference
STP2003QFP
STP3010
STP2014QFP
STP2024QFP
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PDF
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STP2012
Abstract: SuperSPARC STP2016QFP
Text: STP2016 S un M ic r o e l e c t r o n ic s J u ly 1997 Clock-2 Generator DATA SHEET System Clock Generator D e s c r ip t io n The STP2016 Clock-2 Chip generates clock signals for components on the SBus and MBus. The MBus and SBus are used by SPARC processors, such as SuperSPARC™. The MBus is designed for multiprocessing MP , operating at
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OCR Scan
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STP2016
STP2016
64-bit
100-Pin
STP2016Q
STP2012
SuperSPARC
STP2016QFP
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PDF
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mbus 10 application
Abstract: STP2012 TP2018
Text: S un M icroelectronics July 1997 Clock-2 Generator DATA SHEET System Clock Generator D e s c r ip t io n The STP2016 Clock-2 Chip generates clock signals for components on the SBus and MBus. The MBus and SBus are used by SPARC processors, such as SuperSPARC™. The MBus is designed for multiprocessing
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OCR Scan
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STP2016
64-bit
MCLK10
88S88g88
8S3885B
100-Pin
mbus 10 application
STP2012
TP2018
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PDF
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Untitled
Abstract: No abstract text available
Text: S un M icro electro nics July 1997 MSBI DATA SHEET MBus to SBus Interface D e s c r ip t io n The STP2018 MBus to SBus Interface MSBI provides a bus bridge between two different busses used by a number of SPARC microprocessors and controls access to the I/O subsystem. The MBus is designed for
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OCR Scan
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STP2018
64-bit
286-Lead
055-P
25x71
STP2018
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PDF
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STP201
Abstract: No abstract text available
Text: SPA RC T echrdogy Business N ovem ber 1994 S T P 2016 DATA SHEET D C lo c k s G e n e ra to r escription The STP2016 Clock-2 Chip generates clock signals for components on the SBus and MBus. The MBus and SBus are used by SPARC processors, such as SuperSPARC™. The MBus is designed for multi
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OCR Scan
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STP2016
64-bit
STB3DS13-1-894
STP201
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PDF
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sba20
Abstract: mbus master circuit
Text: S un M icro electro nics July 1997 MSI DATA SHEET MBus-to-SBus Interface D e s c r ip t io n The STP2011 MBus-to-SBus Interface MSI provides an interface between the MBus and the SBus and con trols access to the 1 /O subsystem. The MSI consists of two main functional blocks: the Memory Subsystem
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OCR Scan
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STP2011
sba20
mbus master circuit
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PDF
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supersparc
Abstract: STP2003QFP STP3010PGA 805-0086-02 lcd cross reference STP2013 PMC cross reference STP3010 ATM622-S STP2024QFP
Text: S un M icroelectronics July 1997 Data Sheets listed by Marketing Part Cross Reference List M a r k e t in g P a r t 501-4126 Fast Frame Buffer 3D 802-7509-02 501-4127 Fast Frame Buffer (2D) 802-7509-02 SME1040BGA UltraSPARC-ll/ 300 MHz 805-0086-02 SME2411BGFA
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OCR Scan
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SME1040BGA
SME2411BGFA
SME4050BGA
STP1012PGA-85,
STP1021APGA
STP1030A
STP1031
LGA-250
STP1080A
STP1081
supersparc
STP2003QFP
STP3010PGA
805-0086-02
lcd cross reference
STP2013
PMC cross reference
STP3010
ATM622-S
STP2024QFP
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PDF
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M-BUS
Abstract: No abstract text available
Text: S un M ic r o e l e c t r o n ic s July 1997 MSBI MBus to SBus Interface DATA SHEET D e s c r ip t io n The STP2018 MBus to SBus Interface MSBI provides a bus bridge between two different busses used by a number of SPARC microprocessors and controls access to the I/O subsystem. The MBus is designed for multiprocessing (MP),
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OCR Scan
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STP2018
64-bit
STP2018
288-Lead
STP2018TAB
M-BUS
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PDF
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Untitled
Abstract: No abstract text available
Text: STP2018 S un M ic r o e l e c t r o n ic s J u ly 1997 MSBI MBus to SBus Interface DATA SHEET D e s c r ip t io n The STP2018 M Bus to SBus Interface MSBI provides a bus bridge betw een two different busses used by a num ber of SPARC m icroprocessors and controls access to the I /O subsystem. The M Bus is designed for
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OCR Scan
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STP2018
STP2018
64-bit
288-Lead
STP2018TAB
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PDF
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