STP2012
Abstract: SuperSPARC STP2016QFP
Text: STP2016 S un M ic r o e l e c t r o n ic s J u ly 1997 Clock-2 Generator DATA SHEET System Clock Generator D e s c r ip t io n The STP2016 Clock-2 Chip generates clock signals for components on the SBus and MBus. The MBus and SBus are used by SPARC processors, such as SuperSPARC™. The MBus is designed for multiprocessing MP , operating at
|
OCR Scan
|
STP2016
STP2016
64-bit
100-Pin
STP2016Q
STP2012
SuperSPARC
STP2016QFP
|
PDF
|
SuperSPARC
Abstract: Mbus master 250 slave circuit tmx390 STP1091-60
Text: S un M icroelectronics July 1997 Multi-Cache Controller DATA SHEET Integrated Cache Controller for SuperSPARC D e s c r ip t io n The STP1091 is a high-performance external cache controller for the STP1020 SuperSPARC and STP1021 (SuperSPARC-II) microprocessors. It is used when a large secondary cache or an interface to a non-MBus sys
|
OCR Scan
|
STP1091
STP1020
STP1021
33x8k
STP1091PGA-75
STP1091PGA-90
STP1020HS
STP1091
SuperSPARC
Mbus master 250 slave circuit
tmx390
STP1091-60
|
PDF
|
supersparc
Abstract: No abstract text available
Text: Preliminary STP5010A SPARC Technology Business November 1994 5 0 MHz SuperSPARC MBus Module DATA SHEET SuperSPARC Only MBus Module D e s c r i p t io n The STP5010A is one of the members of the SuperSPARC based MBus module products. The STP5010A is designed with the latest high performance superscalar SuperSPARC STP1020A micro
|
OCR Scan
|
STP5010A
STP5010A
STP1020A)
Module-50
STP5010AMBUS-50
STP1020A
supersparc
|
PDF
|
Supersparc
Abstract: IEEE754 STP1021A
Text: STP1021A July 1997 SuperSPARC -II DATA SHEET SPARC v8 32-Bit Superscalar Microprocessor DESCRIPTION The STP1021A is a new member of the SuperSPARC-II family of microprocessor products. Like its predecessors STP1020N, STP1020 and STP1021 this new part is fully SPARC Version 8 compliant and is completely upward compatible with the earlier SPARC Version 7 implementations running over 9,400 SPARC applications and development
|
Original
|
STP1021A
32-Bit
STP1021A
STP1020N,
STP1020
STP1021)
instructionta32
addr18
data50
Supersparc
IEEE754
|
PDF
|
free mbus master
Abstract: SuperSPARC VOLTAGE REGULATOR 78 IEEE754 SS20 STP1021A STP5011D STP5011DMBUS75 M-BUS mbus controllers
Text: STP5011D July 1997 SuperSPARC -II MBus Modules DATA SHEET 75/85 MHz SuperSPARC-II + 1 MB E-Cache DESCRIPTION The STP5011D is the MBus module incorporating the latest SuperSPARC-II microprocessor. This module provides a CPU sub-system with the high performance superscalar SuperSPARC-II microprocessor STP1021A
|
Original
|
STP5011D
STP5011D
STP1021A)
STP1091)
IEEE754
KByte021A.
STP5011DMBUS-75
free mbus master
SuperSPARC
VOLTAGE REGULATOR 78
SS20
STP1021A
STP5011DMBUS75
M-BUS
mbus controllers
|
PDF
|
STP2016
Abstract: SuperSPARC mbus 10 application STP2011 STP2016QFP mbus MCLK11 MOSC STP2012
Text: STP2016 July 1997 Clock-2 Generator System Clock Generator DATA SHEET DESCRIPTION The STP2016 Clock-2 Chip generates clock signals for components on the SBus and MBus. The MBus and SBus are used by SPARC processors, such as SuperSPARC™. The MBus is designed for multiprocessing MP , operating at
|
Original
|
STP2016
STP2016
64-bit
PQFP100
100-Pin
STP2016QFP
SuperSPARC
mbus 10 application
STP2011
STP2016QFP
mbus
MCLK11
MOSC
STP2012
|
PDF
|
mbus 10 application
Abstract: STP2012 TP2018
Text: S un M icroelectronics July 1997 Clock-2 Generator DATA SHEET System Clock Generator D e s c r ip t io n The STP2016 Clock-2 Chip generates clock signals for components on the SBus and MBus. The MBus and SBus are used by SPARC processors, such as SuperSPARC™. The MBus is designed for multiprocessing
|
OCR Scan
|
STP2016
64-bit
MCLK10
88S88g88
8S3885B
100-Pin
mbus 10 application
STP2012
TP2018
|
PDF
|
supersparc
Abstract: HY 1021A Sun STP1021 3AR3 cap 220 htz ADA33
Text: [ f ^ T l r í A C K j S un M i c r o e l e c t r o n i c s July 1997 SuperSPARC“-ll DATA SHEET SPARC v8 32-Bit Superscalar Microprocessor D e s c r ip t io n The STP1021A is a new m em ber of the Su p erSPA R C T I fam ily o f m icroprocessor products. L ik e its predeces
|
OCR Scan
|
STP1021A
STP1020N,
STP1020
STP1021)
cl277
data12
STP1021APGA-85
STP1021APGA-75
supersparc
HY 1021A
Sun STP1021
3AR3
cap 220 htz
ADA33
|
PDF
|
STP201
Abstract: No abstract text available
Text: SPA RC T echrdogy Business N ovem ber 1994 S T P 2016 DATA SHEET D C lo c k s G e n e ra to r escription The STP2016 Clock-2 Chip generates clock signals for components on the SBus and MBus. The MBus and SBus are used by SPARC processors, such as SuperSPARC™. The MBus is designed for multi
|
OCR Scan
|
STP2016
64-bit
STB3DS13-1-894
STP201
|
PDF
|
Untitled
Abstract: No abstract text available
Text: STP1091 S un M ic r o e l e c t r o n ic s J u ly 1997 Multi-Cache Controller DATA SHEET Integrated Cache Controller for SuperSPARC D e s c r ip t io n The STP1091 is a high-perform ance external cache controller for the STP1020 SuperSPARC and STP1021
|
OCR Scan
|
STP1091
STP1091
STP1020
STP1021
33x8k
1091PG
STP1020H
|
PDF
|
SuperSPARC
Abstract: STP1020 mbus sparc IEEE754 STP1021A instruction set Sun SPARC T4 instruction set Sun SPARC T6
Text: ST P 1021A S un M icro electro nics J u ly 1997 SuperSPARC -ll DATA SHEET SPARC v8 32-Bit Superscalar Microprocessor D e s c r ip t io n T h e ST P 1021A is a n e w m em b er o f the SuperSP A R C -II fam ily o f m icro p ro cesso r prod u cts. L ik e its p red eces
|
OCR Scan
|
32-Bit
STP1021A
STP1020N,
STP1020
STP1021)
data50
data32
data49
data31
SuperSPARC
mbus
sparc
IEEE754
instruction set Sun SPARC T4
instruction set Sun SPARC T6
|
PDF
|
supersparc
Abstract: Sun STP1021
Text: S un M icro electro nics July 1997 SuperSPARCT“-ll DATA SHEET SPARC v8 32-Bit Superscalar Microprocessor D e s c r ip t io n The STP1021A is a new member of the SuperSPARC-II family of microprocessor products. Like its predeces sors STP1020N, STP1020 and STP1021 this new part is fully SPARC Version 8 compliant and is completely
|
OCR Scan
|
STP1021A
STP1020N,
STP1020
STP1021)
32-Bit
STP1021APGA-85
STP1021APGA-75
STP1021A
supersparc
Sun STP1021
|
PDF
|
Untitled
Abstract: No abstract text available
Text: Prelimina: SIARCTechnology STP1090A Business January Multi-Cache Controller ,TM DATA. SE ET Integrated Cache Controller for SuperSPARC D e s c r ip t io n The STP1090A is a high-perform ance external cache controller for the STP1020A SuperSPARC and STP1021 (SuperSPARC-II) microprocessors. It is used w hen a large secondary cache or an interface
|
OCR Scan
|
STP1090A
STP1090A
STP1020A
STP1021
33x8k
STP1020H
|
PDF
|
thermal specifications
Abstract: No abstract text available
Text: Modules S T P 5 0 1 1D: SuperSPARC -ll MBus Modules 75/85 MHz SuperSPARC-ll + 1 MB D
|
OCR Scan
|
STP501
thermal specifications
|
PDF
|
|
|
m-bus c#
Abstract: No abstract text available
Text: S T P 5011D S un M ic r o e le c t r o n ic s J u ly 1997 SuperSPARC -ll MBus Modules DATA SHEET 75/85 MHz SuperSPARC-II + 1 MB E-Cache D e s c r ip t io n The STP5011D is the M Bus m odule incorporating the latest SuperSFARC-II microprocessor. This m odule pro
|
OCR Scan
|
5011D
STP5011D
STP1021A)
STP1091)
IEEE754
STP501
STP5011D
m-bus c#
|
PDF
|
K 176 LE, K 561 LN
Abstract: AF34AG cn/A/U 237 BG
Text: Prelim inary SP A R C Business STP1020 A T ech n d o g y June 1995 S u p er S P A R C DATA SHEET TM Highly Integrated 32-Bit RISC Microprocessor D escription The STP1020A is a new member of the SuperSPARC family of microprocessor products. Like its pre decessors STP1020N and ST PI 020 this new part is fully SPARC version 8 compliant and is completely
|
OCR Scan
|
STP1020
32-Bit
STP1020A
STP1020N
K 176 LE, K 561 LN
AF34AG
cn/A/U 237 BG
|
PDF
|
supersparc
Abstract: mbr d type 51 pins connector mbus controllers
Text: Preliminary ^ SPARC Technology Business STP5022B November 1994 Dual 50 MHz SuperSPARC MBus Module DATA SHEET Dual SuperSPARC + E-Cache Module D e s c r i p t io n The STP5022B is a dual SuperSPARC based MBus module. It is designed with the latest high perfor
|
OCR Scan
|
STP5022B
STP5022B
STP1020A)
STP1090A)
STP1020A
STP5022BMBUS-50
STP1020As,
STP1090As,
supersparc
mbr d type 51 pins connector
mbus controllers
|
PDF
|
SuperSPARC
Abstract: M-BUS
Text: Preliminary STP5011B SPARC Technology Business November 1994 60, 50 MHz SuperSPARC MBus Module DATA SHEET SuperSPARC + E-Cache MBus Module D e s c r i p t io n The STP501 IB is one of the members of the SuperSPARC based MBus module products. It is designed
|
OCR Scan
|
STP5011B
STP501
STP1020A)
STP1090A)
STP1020A
an100
STP5011BMB
US-50
SuperSPARC
M-BUS
|
PDF
|
TMx390
Abstract: SuperSPARC STP1020 STP1021A MAD19 STP1091 ADDR02 Mbus master 250 slave circuit stp1090 imad-26
Text: STP1091.frm Page 97 Monday, August 25, 1997 3:08 PM STP1091 July 1997 Multi-Cache Controller DATA SHEET Integrated Cache Controller for SuperSPARC DESCRIPTION The STP1091 is a high-performance external cache controller for the STP1020 SuperSPARC and STP1021 (SuperSPARC-II) microprocessors. It is used when a large secondary cache or an interface to a non-MBus system is required.
|
Original
|
STP1091
STP1091
STP1020
STP1021
33x8k
TMx390
SuperSPARC
STP1020
STP1021A
MAD19
ADDR02
Mbus master 250 slave circuit
stp1090
imad-26
|
PDF
|
Untitled
Abstract: No abstract text available
Text: STP5011D S un M ic r o e l e c t r o n ic s J u ly 1997 SuperSPARC”-ll MBus Modules DATA SHEET 75/85 MHz SuperSPARC-II + 1 MB E-Cache D e s c r ip t io n The STP5011D is the M Bus m odule incorporating the latest SuperSPARC-II microprocessor. This m odule pro
|
OCR Scan
|
STP5011D
STP5011D
STP1021A)
STP1091)
IEEE754
5011DMBUS-75
|
PDF
|
Untitled
Abstract: No abstract text available
Text: STP2016 S un M ic r o e l e c t r o n ic s J u ly 1 9 9 7 Clock-2 Generator System Clock Generator DATA SHEET D e s c r ip t io n The STP2016 Clock-2 Chip generates clock signals for com ponents on the SBus and MBus. The M Bus and SBus are used by SPARC processors, such as SuperSPARC™. The M Bus is designed for multiprocessing
|
OCR Scan
|
STP2016
STP2016
64-bit
100-Pin
TP2016Q
|
PDF
|
tmx390
Abstract: supersparc PM 438 BL capacitor 471 aj7 tmx390x55 tpvc01
Text: STP1091.frm Page 97 Monday, August 25, 1997 3:08 PM S un M ic r o e l e c t r o n ic s July 1997 Multi-Cache Controller DATA SHEET Integrated Cache Controller for SuperSPARC D e s c r ip t io n The STP1091 is a high-performance external cache controller for the STP1020 SuperSPARC and STP1021 (Super
|
OCR Scan
|
STP1091
STP1020
STP1021
33x8k
STP1091PGA-75
STP1091PGA-90
tmx390
supersparc
PM 438 BL
capacitor 471 aj7
tmx390x55
tpvc01
|
PDF
|
6253A
Abstract: supersparc
Text: S un M icroelectronics July 1997 SuperSPARCT"-ll MBus Modules DATA SHEET 75/85 MHz SuperSPARC-II + 1 MB E-Cache D e s c r ip t io n The STP5011D is the M Bus m odule incorporating the latest SuperSPARC-II microprocessor. This m odule pro vides a CPU sub-system with the high perform ance superscalar SuperSPARC-II microprocessor STP1021 A
|
OCR Scan
|
STP5011D
STP1021
STP1091)
IEEE754
STP1021A
STP5011D
6253A
supersparc
|
PDF
|
g31 motherboard repair
Abstract: instruction set Sun SPARC T6 Cache Controller SPARC MA034 Sun Sparc II
Text: P r e lim i n a r\ STP1020A May 1994 SuperSPARC D ATA SH EET Highly Integrated 32-Bit RISC Microprocessor D e s c r ip t io n The STP1020A is a new member of the SuperSPARC family of microprocessor products. Like its predecessors STP1020N and STP1020 this new part is fully SPARC version 8 compliant and is completely upward compatible
|
OCR Scan
|
STP1020A
32-Bit
STP1020A
STP1020N
STP1020)
g31 motherboard repair
instruction set Sun SPARC T6
Cache Controller SPARC
MA034
Sun Sparc II
|
PDF
|