TSB41LV03
Abstract: No abstract text available
Text: TSB12LV01A / TSB12LV01AI Data Manual IEEE 1394-1995 High-Speed Serial-Bus Link-Layer Controller Sourced from: SLLS332A February 2000 Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue
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TSB12LV01A
TSB12LV01AI
SLLS332A
TSB41LV03
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SLLA081
Abstract: paccom ev app abstract
Text: TSB12LV01BĆEP IEEE 1394Ć1995 HighĆSpeed SerialĆBus LinkĆLayer Controller Data Manual July 2002 Mixed Signal Products SGLS123 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications,
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TSB12LV01BEP
SGLS123
SLLA081
paccom ev
app abstract
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Untitled
Abstract: No abstract text available
Text: KSZ9692MPB/KSZ9692XPB Integrated Gigabit Networking and Communications Controller General Description The KSZ9692MPB/KSZ9692XPB is a highly integrated System-on-Chip SoC containing an ARM 922T 32-bit processor and a rich set of peripherals to address the costsensitive, high-performance needs of a wide variety of high
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KSZ9692MPB/KSZ9692XPB
KSZ9692MPB/KSZ9692XPB
32-bit
KSZ9692MPB
M9999-101408-1
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TSB12LV01A
Abstract: TSB12LV01B TSB12LV01BIPZTEP
Text: TSB12LV01BĆEP IEEE 1394Ć1995 HighĆSpeed SerialĆBus LinkĆLayer Controller Data Manual July 2002 Mixed Signal Products SGLS123 Contents Section Title Page 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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TSB12LV01BEP
SGLS123
TSB12LV01A
TSB12LV01B
TSB12LV01BIPZTEP
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SPR154
Abstract: MPC509 ef80 FC-24
Text: Freescale Semiconductor, Inc. MOTOROLA Order this document by MPC509TS/D SEMICONDUCTOR TECHNICAL DATA MPC509 Technical Summary Freescale Semiconductor, Inc. PowerPC MPC509 RISC Microcontroller The MPC509 is a member of the PowerPC Family of reduced instruction set computer RISC microcontrollers (MCUs). The MPC509 implements the 32-bit portion of the PowerPC architecture, which provides 32-bit effective addresses, integer data types of 8, 16, and 32 bits, and floating-point data types
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MPC509TS/D
MPC509
MPC509
32-bit
SPR154
ef80
FC-24
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Realtek PCI LAN 8101L
Abstract: 9346CR RTL8101L RTL8139 BootROM rt8101l lan card RTL8100 RTL8139A RTL8101L modem RTL810 8101L
Text: RTL8101L 1. Features: 1.1 Ethernet Controller Features: wake-up when main power remains off Supports auxiliary power auto-detect, and sets the related capability of power management registers in PCI configuration space Includes a programmable PCI burst size and early Tx/Rx
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RTL8101L
32-bit
93C46
16-bit
MS-026
100LD
14x14x1
LQ100
Realtek PCI LAN 8101L
9346CR
RTL8101L
RTL8139 BootROM
rt8101l
lan card RTL8100
RTL8139A
RTL8101L modem
RTL810
8101L
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ande RY 192
Abstract: ande RY 228 ande RY 227 mov rdn 240 DB14-000121-00
Text: LSI402Z Digital Signal Processor User’s Guide May 2000 Order Number R14014 LSI Logic Confidential This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties
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LSI402Z
R14014
DB15-000131-02,
ande RY 192
ande RY 228
ande RY 227
mov rdn 240
DB14-000121-00
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MPPC 001
Abstract: MPPC 001 ci mppc CADDR15 9711S 9711PT4
Text: 9711 Data Compression Processor Hi/fnTM supplies two of the Internet’s most important raw materials: compression and encryption. Hi/fn is also the world’s first company to put both on a single chip, creating a processor that performs compression and encryption at
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DATA19
DATA20
DATA21
DATA22
DATA23
DATA24
DATA25
DATA26
DATA27
DATA28
MPPC 001
MPPC 001 ci
mppc
CADDR15
9711S
9711PT4
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LSI403LP
Abstract: No abstract text available
Text: Preliminary – Content Subject to Change LSI403LP Digital Signal Processor Preliminary Datasheet The LSI403LP is a 16-bit, fixed-point digital signal processor DSP based on the ZSP 400 DSP core. The LSI403LP contains an entire DSP system on a single chip, and is designed for applications requiring lower
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LSI403LP
16-bit,
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TSB41LV06
Abstract: No abstract text available
Text: TSB42AC3 Data Manual January 2006 CS Peripheral SLLS593A IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue
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TSB42AC3
SLLS593A
MTQF012B
S-PQFP-G100)
MS-026
TSB41LV06
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Untitled
Abstract: No abstract text available
Text: Advance Data Sheet August 1998 LU5M31 Gigabit Ethernet Media Access Controller MAC Overview The LU5M31 is a single-port 1 Gbit/s MAC that incorporates physical coding sublayer (PCS) functionality. The LU5M31 is intended to enhance 10/ 100 Mbits/s Ethernet frame switching, multiple port
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LU5M31
LU5M31
8b/10b
DS98-351LAN
DS97-447LAN)
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Untitled
Abstract: No abstract text available
Text: TSB42AC3 Data Manual January 2004 CS Peripheral SLLS593 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue
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TSB42AC3
SLLS593
SLLS593--January
MTQF012B
S-PQFP-G100)
MS-026
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Untitled
Abstract: No abstract text available
Text: LSI403LP Digital Signal Processor Preliminary Datasheet The LSI403LP is a 16-bit, fixed-point digital signal processor DSP based on the LSI Logic ZSP400 DSP core. The LSI403LP contains an entire DSP system on a single chip, and is designed for applications
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LSI403LP
16-bit,
ZSP400
DB08-000179-00
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Untitled
Abstract: No abstract text available
Text: USER’S GUIDE LSI403LP Digital Signal Processor April 2004 DB15-000230-02 This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation.
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LSI403LP
DB15-000230-02
DB15-000230-02,
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mk48t18
Abstract: LSI53C1510 LSI53C895 LSI53C896 alaska ultra reference design schematics 20405 MFA D3318
Text: TECHNICAL MANUAL LSI53C1510 I2O-Ready PCI RAID Ultra2 SCSI Controller Version 2.2 April 2001 S14024.B This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties
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LSI53C1510
S14024
DB14-000101-02,
LSI53C1510
D-33181
D-85540
mk48t18
LSI53C895
LSI53C896
alaska ultra reference design schematics
20405 MFA
D3318
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83OF
Abstract: gpr 163 TX4964 R4000 R4400 R5000 TX49 R5000 mips MIPS Translation Lookaside Buffer TLB R3000 040106DHQ1
Text: 64 ビット TX System RISC TX49/L3 コア アーキテクチャ Rev 1.0 セミコンダクター社 ● 当社は品質､信頼性の向上に努めておりますが､一般に半導体製品は誤作動した り故障することがあります｡当社半導体製品をご使用いただく場合は､半導体製
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TX49/L3
R4000,
R4400,
R5000
040106DHQ1
83OF
gpr 163
TX4964
R4000
R4400
R5000
TX49
R5000 mips
MIPS Translation Lookaside Buffer TLB R3000
040106DHQ1
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NS7520 Hardware Reference
Abstract: 90000353_G NS7520B-1-I46 NS7520B-1-C55 Errata NS7520 d18 922k D2600N ns7520b NS7520B-1-C36
Text: Part number/version: 90000353_G Release date: September 2007 www.digiembedded.com NS7520 Hardware Reference 2001-2007 Digi International Inc. Printed in the United States of America. All rights reserved. Digi, Digi International, the Digi logo, NetSilicon, a Digi International Company, NET+, NET+OS and
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NS7520
NS7520 Hardware Reference
90000353_G
NS7520B-1-I46
NS7520B-1-C55
Errata
d18 922k
D2600N
ns7520b
NS7520B-1-C36
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transistor SMD BR21
Abstract: SMD Transistor W08 adsp-21369ksz smd w04 74 smd code t04 smd code W06 transistor SMD W06 sMD .v05 smd transistor w04 SMD Transistors w06 56
Text: a SHARC Processors ADSP-21367/ADSP-21368/ADSP-21369 SUMMARY Code compatible with all other members of the SHARC family The ADSP-21367/ADSP-21368/ADSP-21369 are available with a 333 MHz core instruction rate with unique audiocentric peripherals such as the digital audio interface, S/PDIF
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ADSP-21367/ADSP-21368/ADSP-21369
ADSP-21367/ADSP-21368/ADSP-21369
32-bit/40-bit
ADSP-21369KSZ-1A2
ADSP-21368BBP-2A
256-Ball
BP-256
D05267-0-8/06
transistor SMD BR21
SMD Transistor W08
adsp-21369ksz
smd w04 74
smd code t04
smd code W06
transistor SMD W06
sMD .v05
smd transistor w04
SMD Transistors w06 56
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Untitled
Abstract: No abstract text available
Text: CHAPTER 1. 1 PIN FUNCTIONS CLK . Input The clock input. It inputs the SysOut inverted signal from the V r 3000/V r 3000A. (2) CpuD31 to CpuDO . Input/output Being connected to Data31 to DataO of the VR3000/VR3000A, reads write data from the VR3000/VR3000A in the write cycle
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3000/V
CpuD31
Data31
VR3000/VR3000A,
VR3000/VR3000A
MemD31
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SuperSPARC
Abstract: Mbus master 250 slave circuit tmx390 STP1091-60
Text: S un M icroelectronics July 1997 Multi-Cache Controller DATA SHEET Integrated Cache Controller for SuperSPARC D e s c r ip t io n The STP1091 is a high-performance external cache controller for the STP1020 SuperSPARC and STP1021 (SuperSPARC-II) microprocessors. It is used when a large secondary cache or an interface to a non-MBus sys
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STP1091
STP1020
STP1021
33x8k
STP1091PGA-75
STP1091PGA-90
STP1020HS
STP1091
SuperSPARC
Mbus master 250 slave circuit
tmx390
STP1091-60
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SASI
Abstract: cmps a13 grd 07 z32106 Z32100 IRR28 we32100
Text: Zilog P roduct S pecification January 1987 / O D ^ O ^ Z32106 M A U M A T H A C C E L E R A T IO N U N IT DESCRIPTION T he Z32106 M ath A cceleration U nit M AU provides floating-point capability fo r the Z32100 M icroprocessor and is fully com patible with
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Z32106
Z32100
32bit)
64-bit)
80-bit)
32-bit
125-pin
SASI
cmps a13
grd 07
IRR28
we32100
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Z32100
Abstract: z32104
Text: Zilog P r o du c t S p e c i f i c a t i o n J a n u a ry 1987 /oc€>o4 Z32104 D M A C O N TR O LL ER D ESCRIPTIO N T h e Z32104 D M A C o n tro lle r D M A C is a m em ory-m apped p e rip h e ra l device th a t p erfo rm s m em ory-to-m em ory, m em ory-to-peripheral, and
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Z32104
Z32100
32-bit
133-pin
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WE32100
Abstract: ALI m7 101b WE32104
Text: WE 32104 DMA Controller Description The WE 32104 DMA Controller DMAC is a mem ory-mapped peripheral device that performs memory-to-memory, memory fill, mem ory-to-peripheral, and peripheral-tomemory data transfers quickly and efficiently. The DMAC contains specialized hardware that
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32-bit
133-pin
225pF)
WE32100
ALI m7 101b
WE32104
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Untitled
Abstract: No abstract text available
Text: 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT FEATURES: IDT49C460 IDT49C460A IDT49C460B IDT49C460C IDT49C460D IDT49C460E DESCRIPTION: • Fast Detect 10ns max. 12ns (max.) 16ns (max.) 25ns (max.) 30ns (max.) 40ns (max.) Correct 14ns (max.) 18ns (max.)
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32-BIT
IDT49C460
IDT49C460A
IDT49C460B
IDT49C460C
IDT49C460D
IDT49C460E
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