T4C400
Abstract: mt4c4004jdj
Text: M T4C4004J 1 MEG X 4 DRAM l^ldRON DRAM 1 MEG x 4 DRAM QUAD CAS PARITY, FAST PAGE MODE FEATURES _ • Four independent C A S controls, allo w ing in d ivid u al m anipulation to each of the four data In p u t/O u tp ut ports DQ1 through DQ4 . • Offers a single chip solution to byte level parity for 36bit words w hen using 1 M eg x 4 D R A M s for m emory
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T4C4004J
36bit
225mW
024-cycle
MT4C4001JDJ
MT4C4004JDJ
MT4C4004J
MT4C40040
T4C400
mt4c4004jdj
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Untitled
Abstract: No abstract text available
Text: MICR ON S E M I C O N D U C T O R INC b3E D • b l l l S M T D D D V bb ? 51b ■ MRN T4C4004J 1 MEG x 4 DRAM I^HCRON DRAM 1 MEG x 4 DRAM QUAD CAS PARITY, FAST-PAGE-MODE FEATURES _ PIN ASSIGNMENT Top View • Four independent CAS controls, allowing individual
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MT4C4004J
36bit
275mW
A1993,
T4C4001JDJ
T4C4004JDJ
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T4C4004JDJ
Abstract: marking W7F
Text: T4C4004J 1 MEG X 4 DRAM I^ IIC R O N DRAM 1 MEG x 4 DRAM FEATURES _ PIN ASSIGNMENT Top View • Four independent CAS controls, allowing individual manipulation to each of the four data inpu t/output ports (DQ1 through DQ4). • Offers a single chip solution to byte level parity for 36bit words when using 1 M eg x 4 DRAMs for memory
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MT4C4004J
36bit
275mW
024-cycle
24-Pin
MT4C4001JDJ
MT4C4004JDJ
T4C4004JDJ
marking W7F
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U15-U10
Abstract: MT18D236
Text: MT9D136, MT18D236 1 MEG. 2 MEG x 36 DRAM MODULE |V /|ICZRO N DRAM MODULE 1 MEG, 2 MEG x 36 FEATURES PIN ASSIGNMENT Front View • C o m m o n R A S co n tro l p er sid e p in o u t in a 72-p in , sin g le-in -lin e m em o ry m o d u le (SIM M ) • H ig h -p e rfo rm a n ce C M O S silico n -g a te p ro cess.
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MT9D136,
MT18D236
72-Pin
MT1BD236
U15-U10
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Untitled
Abstract: No abstract text available
Text: MICRON M TECHNOLOGY INC SSE D b lllS M R 0QQ433Q T4C4004J 1 MEG X 4 DRAM IC R O N DRAM 1 MEG x 4 DRAM _ • Four independent CAS controls, allowing individual manipulation to each of the four data Input/Output ports DQ1 through DQ4 . • Offers a single chip solution to byte level parity for 36bit words when using 1 Meg x 4 DRAMs for memory
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0QQ433Q
MT4C4004J
36bit
225mW
024-cycle
00Q4343
T4C4001JDJ
T4C4004JDJ
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Untitled
Abstract: No abstract text available
Text: T4C4004J 1 MEG X 4 DRAM M IC R O N I TECHNOLOGY. INC. 1 MEG x 4 DRAM DRAM 5V, QUAD CAS PARITY, FAST PAGE MODE _ PIN ASSIG N M EN T Top View • Four independent CAS controls, allowing individual manipulation to each of the four data inpu t/output ports (DQ1 through DQ4).
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MT4C4004J
36-bit
225mW
024-cycle
D015204
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