V962PBC Search Results

AD12

Abstract: AD14 AD30 V292PBC V962PBC V962PBC-33 V962PBC-40 V96BMC
Contextual Info: V962PBC Rev. B2 LOCAL BUS TO PCI BRIDGE FOR DE-MULTIPLEXED A/D PROCESSORS • Dual bi-directional address space remapping • Glueless interface between Intel i960 Cx/Hx processors and PCI bus • On-the-fly byte order endian conversion • Fully compliant with PCI 2.1 specification

Contextual Info: • V yf V962PBC f ^ « K O • Rev. B1 LOCAL BUS TO PCI BRIDGE FOR i960 Cx/Hx PROCESSORS / * 5 • Glueless interface between ¡960Cx/Hx processors and the PCI bus • 2 channel DMA controller • Bi-directional mailboxes w/doorbell interrupts • Large, 576-byte FIFOs using V 3 ’s unique

Contextual Info: V962PBC S LOCAL BUS TO PCI BRIDGE FOR DE-MULTIPLEXED A/D PROCESSORS • Glueless interface between Intel ¡960 Cx/Hx processors and PCI bus • Fully compliant with PCI 2.1 specification • Configurable for primary master, bus master, or target operation

V292PBC

Abstract: V960PBC V961PBC V962PBC
Contextual Info: V3 Technical Note July 10, 1998 Stepping Change Notification: PBC ‘B2’ Step to EPC ‘A0’ Step Rev 1.30 Includes the V292PBC, V960PBC, V961PBC, and V962PBC EPC ‘A0’ was previously referred to as stepping PBC ‘C0’ The PBC is currently shipping at stepping level ‘B2’. In Q2 1997 V3 Semiconductor

i486

Abstract: intel i486 i486 bus interface V3 Semiconductor V962PBC V96BMC i486 intel
Contextual Info: Application Note: Introduction to interfacing the Intel i486 Processor to the PCI Bus 1. Objective This application note describes how to interface the ubiquitous Intel i486 microprocessor with the V3 Semiconductor’s V962PBC PBC PCI bridge and V96BMC (BMC) DRAM

HD64572

Abstract: V962PBC i960-Cx Hitachi DSA0013
Contextual Info: Application Note: Introduction to interfacing the Hitachi SCA-II to the PCI Bus Objective This application note describes how to interface 32-bit Hitachi HD64572 Advanced Serial Communications Adapter SCA-II with the V962PBC (PBC) PCI bridge . Target applications include PCI based adapter

PPC401GF

Abstract: V292PBC V960PBC V960PBC-33 V961PBC V961PBC-33 V961PBC-40 V962PBC V962PBC-33 V962PBC-40
Contextual Info: VxxxPBC Rev. B2 LOCAL BUS TO PCI BRIDGE CONTROLLERS Data Sheet Addendum • I2OTM ready hardware messaging unit • Large, 576-byte FIFOs using V3’s unique DYNAMIC BANDWIDTH ALLOCATION architecture • 2 channel DMA controller • 33MHz and 40MHz local bus versions available

V96SSC25LP

Contextual Info: ‘ÌOOMEOO 0 0 0 0 3 0 3 ISA V96SSC • * * ▼ / Rev. BO HIGH-INTEGRATION SYSTEM CONTROLLER FOR ¡960 Sx/Jx AND PowerPC 401 Gx PROCESSORS • Direct interface to ¡960Sx/Jx and PPC401Gx processors • High-performance burst DRAM controller • Two-channel fly-by DMA controller

Contextual Info: V360EPC Rev. A0 LOCAL BUS TO PCI BRIDGE FOR DE-MULTIPLEXED A/D PROCESSORS • Glueless interface to i960Cx/Hx and AMD29030/40 processors • On-the-fly byte order endian conversion • I2O ATU and messaging unit including hardware controlled circular queues

Signal Path Designer

Contextual Info: V96BMC Rev D HIGH PERFORMANCE BURST DRAM CONTROLLER FOR i960 Cx/Hx/Jx and PowerPC 401Gx PROCESSORS BLOCK DIAGRAM • Direct interface to i960Cx/Hx/Jx processors • 2Kbyte burst transaction support • SRAM performance achieved with DRAM • Designed to work with V961PBC and

Contextual Info: ^004200 □□□□102 MST • V961PBC •" V Rev. B1 LOCAL BUS TO PCI BRIDGE FOR i960 Jx AND PowerPC 401 Gx PROCESSORS " • Glueless interface between ¡960Jx, PPC401 Gx processors and the PCI bus • Large, 576-byte FIFOs using V3's unique D y n a m ic B a n d w id t h A l l o c a t i o n ™ architecture

Contextual Info: T 0 Q 4 E D 0 D D D O H b b 212 V292BMC Rev. D HIGH PERFORMANCE BURST DRAM CONTROLLER :.V “ FOR Am29030/40 PROCESSORS • Pin/Software compatible with earlier V292BMC. • Integrated Page Cache Management. • Direct interfaces to Am29030/40 processors.

ld18 st

Abstract: tvp ul 137 AD14 V292PBC V360EPC V360EPC-33 V360EPC-50 V962PBC V96BMC
Contextual Info: V‘ 5f V360EPC Rev. AO LOCAL BUS TO PCI BRIDGE FOR DE-MULTIPLEXED A/D PROCESSORS &M|£ 0 * 1Glueless ¡960Cx/Hx and AMD29030/40 processors interface 1Large, 640-byte FIFOs using V 3’s unique D y n a m ic B a n d w id t h A l l o c a t io n architecture

V360EPC

Abstract: 1gg7 Extended Sector Remapper V3 Semiconductor V350EPC design of dma controller using vhdl eeprom programmer schematic 24c02 V292PBC V960PBC V961PBC
Contextual Info: Chapter 1 Introduction In a very short period of tim e the PCI bus standard has moved beyond the PC to become the most w idely accepted high-performance bus standard for embedded applications. As a leader in providing chipset solutions for high-end embedded applications, V3 Sem iconductor

Contextual Info: • TD042DD 0000132 V292PBC 117 Rev. B1 LOCAL BUS TO PCI BRIDGE FOR Am29K PROCESSORS '« IC O * ” ’ • Glueless interface between Am29030/40 processors and the PCI bus • Large, 576-byte FIFOs using V3’s unique D y n a m ic B a n d w id t h A l l o c a t i o n ™ architecture

PJ3N

Contextual Info: . . y lf • * ▼ • =1004200 0 0 0 0 0 2 1 V96DPC f « 450 ■ Rev. B1 LOCAL BUS TO PCI BRIDGE FOR i960 Cx/Hx/Jx/Sx AND PowerPC 40lGx PROCESSORS • Glueless interface between i960Sx/Jx/Cx/Hx, PPC401 Gx processors and two PCI buses • On-the-fly byte order endian conversion

AD30

Abstract: V292PBC V360EPC V360EPC-33 V360EPC-50 V962PBC V96BMC V360EPC-33LP REV A1
Contextual Info: V360EPC Rev. A0 / A1 LOCAL BUS TO PCI BRIDGE FOR DE-MULTIPLEXED A/D PROCESSORS • Glueless interface to i960Cx/Hx and AMD29030/40 processors • On-the-fly byte order endian conversion • I2O ATU and messaging unit including hardware controlled circular queues

Contextual Info: V360EPC v -mam* * # if T Rev. AO LOCAL BUS TO PCI BRIDGE FOR DE-MULTIPLEXED A/D PROCESSORS A „v * ' « I C O * 1Glueless ¡960Cx/Hx and AMD29030/40 processors interface 1120 ready hardware messaging unit 12 channel DMA controller plus Multiprocessor DMA chaining and demand mode DMA

Contextual Info: Chapter 1 Introduction In a very short period of tim e the PCI bus standard has moved beyond the PC to become the most w idely accepted high-perform ance bus standard for embedded applications. As a leader in providing chipset solutions for high-end embedded applications, V3 Sem iconductor

Contextual Info: •iOONSna 0 0 0 0 0 4 7 V960PBC V 313 Rev. B1 LOCAL BUS TO PCI BRIDGE FOR i960 Sx PROCESSORS “ • Glueless interface between ¡960Sx processors and the PCI bus • Large, 576-byte FIFOs using V3’s unique D y n a m ic B a n d w id t h A l l o c a t i o n architecture

AMD2930

Abstract: LDO, ld12
Contextual Info: V360EPC Rev. AO LOCAL BUS TO PCI BRIDGE FOR DE-MULTIPLEXED A/D PROCESSORS Glueless interface to ¡960Cx/Hx and AMD29030/40 processors Configurable for primary master, bus master or target operation. On-the-fly byte order endian conversion l20 ATU and messaging unit including

Contextual Info: • S00M200 V96BMC jj ; v D000M54 STO Rev. D HIGH PERFORMANCE BURST DRAM CONTROLLER - FOR i960Cx/Hx/Jx PROCESSORS • Pin/Software compatible with earlier V96BMC. • Integrated Page Cache Management. • Direct interfaces to i960Cx/Hx/Jx processors. • 2Kbyte burst transaction support.

Contextual Info: TG04200 if QQQD117 V 9 6 2 P B C SÔQ Rev. B1 LOCAL BUS TO PCI BRIDGE FOR i960 Cx/Hx PROCESSORS » Ic0* v • Glueless interface between i960Cx/Hx processors and the PCI bus • 2 channel DMA controller • Bi-directional mailboxes w/doorbell interrupts • Large, 576-byte FIFOs using V3’s unique