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    TE Connectivity SLDE-210-B-10-A-0-A1188

    SLDE 210 B 10 A 0 A1188
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    TE Connectivity SLDE-410-C-10-A-0-A1188

    SLDE 410 C 10 A 0 A1188
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    DigiKey SLDE-410-C-10-A-0-A1188 Bulk 38
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    TE Connectivity SLDE-205-B-10-A-0-A1188

    SLDE 205 B 10 A 0 A1188
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    DigiKey SLDE-205-B-10-A-0-A1188 Bulk 80
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    TE Connectivity SLDE-325-B-10-A-0-A1188

    SLDE 325 B 10 A 0 A1188
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    DigiKey SLDE-325-B-10-A-0-A1188 Bulk 42
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    TE Connectivity SLDE-210-C-10-A-0-A1188

    SLDE 210 C 10 A 0 A1188
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    DigiKey SLDE-210-C-10-A-0-A1188 Bulk 63
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    A0A11 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    SM81600E

    Abstract: IS42SM16800E IS42SM81600E IS42SM16800E-7TLI IS42SM32400E IS42SM32400E-7T IS42SM16800E-7BLI
    Text: IS42SM81600E / IS42SM16800E / IS42SM32400E IS42RM81600E / IS42RM16800E / IS42RM32400E 16Mx8, 8Mx16, 4Mx32 128Mb Mobile Synchronous DRAM APRIL 2011 DESCRIPTION FEATURES • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access and precharge


    Original     		PDF IS42SM81600E IS42SM16800E IS42SM32400E IS42RM81600E IS42RM16800E IS42RM32400E 16Mx8, 8Mx16, 4Mx32 128Mb SM81600E IS42SM16800E-7TLI IS42SM32400E-7T IS42SM16800E-7BLI

    IS42VS16100E

    Abstract: 42VS16100E IS42VS16100E-75BLI
    Text: IS42VS16100E 512K Words x 16 Bits x 2 Banks 16Mb SYNCHRONOUS DYNAMIC RAM FEATURES • Clock frequency: 133, 100, 83 MHz • Fully synchronous; all signals referenced to a positive clock edge • Two banks can be operated simultaneously and independently • Dual internal bank controlled by A11


    Original     		PDF IS42VS16100E 4000-mil 60-ball 400-mil IS42VS16100E 42VS16100E IS42VS16100E-75BLI

    Untitled

    Abstract: No abstract text available
    Text: CMS4A16LAx–75Ex 128M 8Mx16 Low Power SDRAM Revision 0.5 May. 2007 Rev. 0.5, May. ‘07 CMS4A16LAx–75Ex Document Title 128M(8Mx16) Low Power SDRAM Revision History Revision No. History Draft date Remark Preliminary 0.0 Initial Draft Apr.25th, 2005 0.1


    Original     		PDF CMS4A16LAx 8Mx16) 160ns 350uA 400uA

    AS4SD32M16

    Abstract: No abstract text available
    Text: SDRAM AS4SD32M16 512Mb: 32 Meg x 16 SDRAM PIN ASSIGNMENT Top View Synchronous DRAM Memory 54-Pin TSOP FEATURES • Full Military temp (-55°C to 125°C) processing available • Configuration: 32 Meg x 16 (8 Meg x 16 x 4 banks) • Fully synchronous; all signals registered on positive


    Original     		PDF AS4SD32M16 512Mb: 192-cycle -40oC -55oC 125oC AS4SD32M16

    Untitled

    Abstract: No abstract text available
    Text: SDRAM AS4SD8M16 128 Mb: 8 Meg x 16 SDRAM PIN ASSIGNMENT Top View Synchronous DRAM Memory 54-Pin TSOP FEATURES • • • • • • • • • • • • • • Full Military temp (-55°C to 125°C) processing available Copper lead frame option for enhanced reliability


    Original     		PDF AS4SD8M16 096-cycle -40oC -55oC 125oC AS4SD8M16

    IS42S32400D

    Abstract: 42S32400D is42s32400d-6bli IS42S32400D-7TLI
    Text: IS42S32400D 4Meg x 32 128-MBIT SYNCHRONOUS DRAM FEATURES • Clock frequency: 166, 143, 125, 100 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge MARCH 2009 OVERVIEW ISSI's 128Mb Synchronous DRAM achieves high-speed


    Original     		PDF IS42S32400D 128-MBIT 128Mb rS32400D-7TI 86-Pin IS42S32400D-7TLI IS42S32400D-7BI IS42S32400D 42S32400D is42s32400d-6bli IS42S32400D-7TLI

    DDR200

    Abstract: DDR266A DDR266B IBMN612404GT3B IBMN612804GT3B IBMN62540 IBMN62580 128MB PC266
    Text: IBMN612404GT3B IBMN612804GT3B 128Mb Double Data Rate Synchronous DRAM Preliminary Features CAS Latency and Frequency CAS Latency 2 2.5 Maximum Operating Frequency MHz * DDR266A (7N) DDR266B (75N) DDR200 (8N) 133 143 100 133 100 125 * Values are nominal (exact tCK should be used).


    Original     		PDF IBMN612404GT3B IBMN612804GT3B 128Mb DDR266A DDR266B DDR200 06K0566 F39350B DDR200 DDR266A DDR266B IBMN612404GT3B IBMN612804GT3B IBMN62540 IBMN62580 128MB PC266

    Untitled

    Abstract: No abstract text available
    Text: . IBM13M64734CCA 64M x 72 2-Bank Registered/Buffered SDRAM Module Features • 168-Pin Registered 8-Byte Dual In-Line Memory Module • 64Mx72 Synchronous DRAM DIMM • Performance: -260 Device Latency fCK Clock Frequency tAC Clock Access Time 2 -360 -360 Units


    Original     		PDF IBM13M64734CCA 168-Pin 64Mx72 66/100MHz PC100 09K3884 F38744

    NT5DS8M16FS-5T

    Abstract: NT5DS8M16FS-6K NT5DS8
    Text: NT5DS8M16FT NT5DS8M16FS 128Mb DDR SDRAM Features • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Burst lengths: 2, 4, or 8 • CAS Latency: 2 & 2.5 for 6K, 2, 2.5, & 3 for 5T


    Original     		PDF NT5DS8M16FT NT5DS8M16FS 128Mb NT5DS8M16FS-5T NT5DS8M16FS-6K NT5DS8

    ba1s

    Abstract: No abstract text available
    Text: IS43LR32400E Advanced Information 1M x 32Bits x 4Banks Mobile DDR SDRAM Description The IS43LR32400E is 134,217,728 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 1,048,576 words x 32 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The address lines are multiplexed with the Data


    Original     		PDF IS43LR32400E 32Bits IS43LR32400E Figure38 90Ball -25oC 4Mx32 IS43LR32400E-6BLE ba1s

    Nanya nt5ds8m16fs

    Abstract: NT5DS8M16FS NT5DS8M16FT-5TI NT5DS8M16FS-5T DDR333 DDR400 NT5DS8M16 NT5DS8M16FT-6KI NT5DS8M16FT
    Text: NT5DS8M16FT-5TI NT5DS8M16FS-5TI NT5DS8M16FT-6KI NT5DS8M16FS-6KI 128Mb DDR SDRAM Features • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Burst lengths: 2, 4, or 8


    Original     		PDF NT5DS8M16FT-5TI NT5DS8M16FS-5TI NT5DS8M16FT-6KI NT5DS8M16FS-6KI 128Mb Nanya nt5ds8m16fs NT5DS8M16FS NT5DS8M16FT-5TI NT5DS8M16FS-5T DDR333 DDR400 NT5DS8M16 NT5DS8M16FT-6KI NT5DS8M16FT

    NT5DS8M16FS-5T

    Abstract: NT5DS8M16FS-6K NT5DS8M16 NT5DS8M16FS
    Text: NT5DS8M16FT NT5DS8M16FS 128Mb DDR SDRAM Features • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Burst lengths: 2, 4, or 8 • CAS Latency: 2 & 2.5 for 6K, 2, 2.5, & 3 for 5T


    Original     		PDF NT5DS8M16FT NT5DS8M16FS 128Mb NT5DS8M16FS-5T NT5DS8M16FS-6K NT5DS8M16 NT5DS8M16FS

    NT5SV8M16FS

    Abstract: Nanya NT5SV8M16FS NT5SV8M16FS-75BI Nanya NT5SV8M16FS-75Bi NT5SV8M16FS-6KI NT5SV8M16FT NT5SV8M16FT-6KI nt5sv8m16fs-6k 54-PIN NT5SV8M16FT-6K
    Text: NT5SV8M16FT-6KI NT5SV8M16FS-6KI NT5SV8M16FT-75BI NT5SV8M16FS-75BI 128Mb Synchronous DRAM • • • • • • • • • • • • Features • High Performance: Maximum Operating Speed CAS Latency PC166 6KI PC133 (75BI) 2 7.5 10 ns 3 6 7.5 ns •


    Original     		PDF NT5SV8M16FT-6KI NT5SV8M16FS-6KI NT5SV8M16FT-75BI NT5SV8M16FS-75BI 128Mb PC166 PC133 NT5SV8M16FS Nanya NT5SV8M16FS NT5SV8M16FS-75BI Nanya NT5SV8M16FS-75Bi NT5SV8M16FS-6KI NT5SV8M16FT NT5SV8M16FT-6KI nt5sv8m16fs-6k 54-PIN NT5SV8M16FT-6K

    NCC equivalent

    Abstract: No abstract text available
    Text: TMS29F400T, TMS29F400B 524288 BY 8-BIT/262144 BY 16-BIT FLASH M EMORIES • I • Single Power Supply Supports 5 V ± 10% Read/Write Operation I I • Organization . . . I • Array-Blocking Architecture - One 16K-Byte/One 8K-Word Boot Sector - Two 8K-Byte/4K-Word Parameter Sectors


    OCR Scan     		PDF TMS29F400T, TMS29F400B 8-BIT/262144 16-BIT SMJS843A 44-Pin 48-Pin 8-Blf/262144 NCC equivalent

    Untitled

    Abstract: No abstract text available
    Text: TO SHIBA THMY644071EG-10 TENTATIVE TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT 4,194,304-WORD BY 64-BIT SYNCHRONOUS DRAM MODULE DESCRIPTION The THMY644071EG is a 4,194,304-word by 64-bit synchronous dynamic RAM module consisting of four TC59S6416FT DRAMs and an unbuffer on a printed circuit board.


    OCR Scan     		PDF THMY644071EG-10 304-WORD 64-BIT THMY644071EG TC59S6416FT THMY644071

    TC5116400

    Abstract: tc5116400csj 300D1 toshiba RAS-25
    Text: INTEGRATED TOSHIBA TO SH IBA M O S DIGITAL NTEGRATED CIRCUIT CIRCUIT TECHNICAL T C 5 1 16 4 0 0 C S J / C S T - 4 0 T C 5 1 1 6 4 0 0 C S J / C S T - 50 T C 5 1 1 6 4 0 0 CSJ / C S T * 60 DATA SILICON GATE C M O S TENTATIVE D ATA 4,194,304 W O R D x 4 BIT D Y N A M IC R A M


    OCR Scan     		PDF TC5116400CSJ/CST 300mil) 400CSJ/C TC5116400 CSJ/CST-40 CSJ/CST-50 tc5116400csj 300D1 toshiba RAS-25

    TLCS-47

    Abstract: No abstract text available
    Text: TOSHIBA TMP47P452VN, TMP47P452W For program operation, the programming is achieved by using with EPROM programm er TMM2764AD type and adapter socket (BM1120, BM1121). CMOS 4-Bit Microcontroller TMP47P452VN, TMP47P452VF The 47P452V is the OTP microcontroller with 32kbits PROM.


    OCR Scan     		PDF TMP47P452VN, TMP47P452W TMP47P452VF 47P452V 32kbits TMM2764AD BM1120, BM1121) QFP44 TLCS-47

    r2a3

    Abstract: r1a10 M1367 M4589
    Text: TOSHIBA THMY728010BEG-80L TENTATIVE TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT 8,388,608-WORD BY 72-BIT SYNCHRONOUS D RA M MODULE DESCRIPTION The THMY728010BEG is a 8,388,608-word by 72-bit synchronous dynamic RAM module consisting of nine TC59S6408BFTL DRAMs and PLL/Registers on a printed circuit board.


    OCR Scan     		PDF THMY728010BEG-80L THMY728010BEG 608-word 72-bit TC59S6408BFTL 72-bit r2a3 r1a10 M1367 M4589

    Untitled

    Abstract: No abstract text available
    Text: TL16PNP100A STANDALONE PLUG-AND-PLAY PnP CONTROLLER SLLS200B - MARCH 1995 - REVISED MARCH 1996 PnP Card Autoconfiguration Sequence Compliant Supports TVvo Logical Devices Decodes 10-Bit I/O Address Location With Programmable 1-, 2-, 4-, 8-, 16-Byte Block


    OCR Scan     		PDF TL16PNP100A SLLS200B 10-Bit 16-Byte ST93C56/66 44-Pin 48-Pin i--11 h--11 16-bit

    Untitled

    Abstract: No abstract text available
    Text: TOSHIBA TC51V16400BST-60/70 PRELIMINARY 4,194,304 WORD X 4 BIT DYNAMIC RAM Description TheTC 51V16400B ST is the new generation dynamic RAM organized 4,194,304 word by 4 bits. T heTC 51V16400B ST uti­ lizes Toshiba's CM O S silicon gate process technology as well as advanced circuit techniques to provide wide operating mar­


    OCR Scan     		PDF TC51V16400BST-60/70 51V16400B TC51V16400BST 300mil)

    2269H

    Abstract: No abstract text available
    Text: TOSHIBA THMY7216C1EG-80H TENTATIVE TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT 16,777,216-WORD BY 72-BIT SYNCHRONOUS DRAM MODULE DESCRIPTION The THMY7216C1EG is a 16,777,216-word by 72-bit synchronous dynamic RAM module consisting of 18 TC59S6408FT DRAMs and an unbuffer on a printed circuit board.


    OCR Scan     		PDF THMY7216C1EG-80H 216-WORD 72-BIT THMY7216C1EG TC59S6408FT 72-bit THMY7216C1EG) 2269H

    2332 eprom

    Abstract: PIN-20 IC DIAGRAM 2332 rom 2732A eprom
    Text: TMS2332 4096-WORD BY 8-BIT READ-ONLY MEMORY SEPTEMBER 1984 - REVISED NOVEMBER 1985 4 0 9 6 X 8 Organization N PACKAGE All Inputs and Outputs TTL Compatible TOP VIEW A 7 C 1 ^ 2 4 3 v Cc A6£ 2 23 3 A 8 A5 £ 3 22 > 9 Fully Static (No Clocks. No Refresh)


    OCR Scan     		PDF TMS2332 4096-WORD 2332 eprom PIN-20 IC DIAGRAM 2332 rom 2732A eprom

    TCK-1000

    Abstract: D038 toshiba M7
    Text: TO SH IBA THM Y6480F1 BEG-80 TEN TA TIVE TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT 8,388, 6 O8-W O RD B Y 64-BIT SYN CH R O N O U S DRAM M ODULE D ESCRIPTIO N The THMY6480F1BEG is a 8,388,608-word by 64-bit synchronous dynamic RAM module consisting of eight TC59S6408BFT DRAMs and an unbuffer on a printed circuit board.


    OCR Scan     		PDF Y6480F1 BEG-80 64-BIT THMY6480F1BEG 608-word TC59S6408BFT 64-bit THMY6480F1 TCK-1000 D038 toshiba M7

    Untitled

    Abstract: No abstract text available
    Text: TMS416160, TMS416160P 1 048 576-WORD BY 16-BIT HIGH-SPEED DYNAMIC RANDOM-ACCESS MEMORIES SMKS660-DECEMBER 1992 Organization. . . 1 048 576 x 16 RE P A C K A G E t DC P A C K AG E t TOP VIEW (TOP VIEW) Single 5-V Supply (10% Tolerance) '416160/P-60 '416160/P-70


    OCR Scan     		PDF TMS416160, TMS416160P 576-WORD 16-BIT SMKS660-DECEMBER 416160/P-60 416160/P-70 416160/P-80