A7A17
Abstract: D56-D63 burndy CONNECTOR 124
Text: CYM7432 PRELIMINARY 256K PentiumtĆCompatible Cache Module Features D D D D D D D D Functional Description 256ĆKbyte secondary cache module organized as 32K by 64 Ideal for Intelt PentiumĆbased sysĆ tems and systems with 64Ćbit data Operates with 60Ć and 66ĆMHz PenĆ
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CYM7432
256Kbyte
64bit
66MHz
160position
CYM7432
A7A17
D56-D63
burndy CONNECTOR 124
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J32CG
Abstract: 61a3 mosfet BCM5461KFB 61a3 58A6 bcm5461 60F10 L32SD DQ27152 A26B4
Text: 1 2 4 3 5 6 7 TABLE OF CONTENTS F F PAGE 02 - BLOCK DIAGRAM PAGE 03 - 750GX ADDRESS/DATA BUSSES PAGE 04 - 750GX CONTROLS AND GROUND PAGE 05 - 750GX POWER AND DECOUPLING PAGE 06 - TSI108 PROCESSOR BUS INTERFACE PAGE 07 - TSI108 MEMORY INTERFACE PAGE 08 - DDR2 DIMM CONNECTOR SLOT 0
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750GX
TSI108
RS232
NC7SZ00
J32CG
61a3 mosfet
BCM5461KFB
61a3
58A6
bcm5461
60F10
L32SD
DQ27152
A26B4
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PDF
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82497
Abstract: cache controller intel 82496 BGT Q 900 A18 OE T10 t187 intel 82496 apic s09 290446 82489dx 82496 a82496
Text: D Pentium Processor Family Developer’s Manual Volume 2: 82496/82497/82498 Cache Controller and 82491/82492/82493 Cache SRAM NOTE: The Pentium® Processor Family Developer’s Manual consists of three books: Pentium® Processor Order Number 241428; the
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Intel486TM
1-55512-237-X
1-55512-240-X
82497
cache controller intel 82496
BGT Q 900 A18 OE T10
t187
intel 82496
apic s09
290446
82489dx
82496
a82496
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PDF
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Untitled
Abstract: No abstract text available
Text: AT28MC020 Features • • • • • • • • • • • Fast Read Access Time -150 ns Automatic Page W rite Operation Internal Address and Data Latches fo r 128 Bytes Internal Control Timer Fast Write Cycle Time Page W rite Cycle Time -1 0 ms maximum
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AT28MC020
AT28MC020-25ZC
AT28MC020-25ZMB
AT28MC020-25ZM
AT28MC020-25ZI
AT28MC020-20ZMB
AT28MC020-20ZM
AT28MC020-20ZI
AT28MC020-15ZC
AT28MC020-15ZMB
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Untitled
Abstract: No abstract text available
Text: AT28MC020 Features • • • • • • • • • • • Fast Read Access Time -150 ns Automatic Page Write Operation Internal Address and Data Latches for 128 Bytes Internal Control Timer Fast Write Cycle Time Page Write Cycle Time -10 ms maximum 1 to 128 Byte Page Write Operation
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OCR Scan
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AT28MC020
M5004
Military/883C
AT28MC020-20ZC
AT28MC020-20ZI
AT28MC020-20ZM
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PDF
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Untitled
Abstract: No abstract text available
Text: AT28MC020 Features • • • • • • • • • • • Fast Read Access Time -150 ns Automatic Page Write Operation Internal Address and Data Latches for 128 Bytes Internal Control Timer Fast Write Cycle Time Page Write Cycle Time -1 0 ms maximum 1 to 128 Byte Page Write Operation
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OCR Scan
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AT28MC020
AT28MC020MC020-20ZMB
M5004
Military/883C
AT28MC020-25ZC
AT28MC020-25ZI
AT28MC020-25ZM
AT28MC020-25ZMB
AT28MC020-20ZM
AT28MC020-20ZI
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PDF
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ZD6A
Abstract: TAG03 82497 3 PP 03 L 04 14-3-221 cfa24 cache controller intel 82496 zd-5a
Text: in te i CHAPTER 14 ELECTRICAL SPECIFICATIONS 14.1. ABSOLUTE MAXIMUM RATINGS Table 14-1 provides environmental stress ratings for the chip set com ponents. Functional operation at the absolute maximum and minimum is not implied or guaranteed. Extended exposure to maximum ratings may affect device reliability. Further, precautions should be
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ZD6A
Abstract: t177 ZR7a cache controller intel 82496
Text: in te i CHAPTER 7 ELECTRICAL SPECIFICATIONS 7.1. POWER AND GROUND For clean on-chip power distribution, the Pentium processor has 50 Vc c power and 49 Vss (ground) inputs. The 82496 Cache Controller has 56 V cc (power) and 67 V ss (ground) inputs and the 8 2 4 9 1 Cache SRAM has 9 V q c (power) and 9 VSs (ground) inputs. Power and
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OCR Scan
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Controller/82491
ZD6A
t177
ZR7a
cache controller intel 82496
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