ACT1020
Abstract: JH05 MARKING CODE N-CHANNEL MOS FIELD EFFECT TRANSISTOR 44 pin actel 1020b JEDEC-A113 ACTEL 1020B ACP55 smd U1p Jl03 JL-03
Text: Quality & Reliability Guide February 2001 2001 Actel Corporation All Rights Reserved. Actel and the Actel logo are trademarks of Actel Corporation. All other brand or product names are the property of their respective owners. Contents 1. Overview of Actel’s Quality and Reliability Guide . . . . . . . . . . . . . . . . . . . .1
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A1280XL-CQ172C
Abstract: A1280XLCQ172 RH1020CQ84V rh1280 trim socket FPQ-256 0B11000000 FPQ Package PC MOTHERBOARD repair MANUAL aic6260 ACTEL 1020B
Text: RadHard/RadTolerant Programming Guide Windows and UNIX® Environments RadHard/RadTolerant Programming Guide Windows and UNIX Environments Actel Corporation, Sunnyvale, CA 94086 1997 Actel Corporation. All rights reserved. Printed in the United States of America
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ACTEL 1020B
Abstract: 222F A1010 A1020 A1280 F012 ACTIVATOR 2s activator1 APS-259
Text: APS Programming System User’s Guide Windows & UNIX® Environments Actel Corporation, Sunnyvale, CA 94086 1996 Actel Corporation. All rights reserved. Part Number: 5029032-0 June 1996 No part of this document may be copied or reproduced in any form or by any
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actel 1240a
Abstract: TI1139 UI02 1280xl actel 1240xl 132 pga UJ-01 U1H-18 110E06 SI 1020A Actel A1225
Text: Actel Device Reliability Report Actel’s field programmable gate arrays FPGAs are currently available in five product families—ACT 1, ACT 2, 1200XL, 3200DX, and ACT 3. The ACT 1 family consists of the A1010 and A1020, which are 1200- and 2000-gate FPGAs,
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1200XL,
3200DX,
A1010
A1020,
2000-gate
A1225,
A1240,
A1280
1200XL
A1225XL,
actel 1240a
TI1139
UI02
1280xl
actel 1240xl 132 pga
UJ-01
U1H-18
110E06
SI 1020A
Actel A1225
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13001 s
Abstract: 13001 datasheet 13001 JL-01 ACTEL 1020B RTSX32 B 13001 RTSX16 42MX09 1280A
Text: Actel 4th Quarter 2000 Reliability Report 1 Table of Contents Page Reliability Test Matrix • Test Methods and Conditions Failure Rates • Failure Rates FITs Based For Current Process Data • Mean Time Between Failure (MTBF) For Current Process Data 2
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1225XL,
1240XL,
1280XL,
A1415,
A1425,
14100BP,
32140DX,
32200DX
13001 s
13001 datasheet
13001
JL-01
ACTEL 1020B
RTSX32
B 13001
RTSX16
42MX09
1280A
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RT54SX72SCQ208
Abstract: rt1280 RT54SX32S-CQ208 RTSX72 RT1020-CQ84B aircraft logic gates RTSX72S RT1425 RT14100 RH1020-CQ84V
Text: Civilian/Scientific Exploration Actel FPGAs for Space Applications Uncompromising in the Extreme Deep Space I Device Speed Grade Gates Logic Modules Available I/Os DSCC SMD Mars Surveyor RadHard RH1020-CQ84V Std 4,000 547 69 5962F90965 RH1280-CQ172V Std 16,000
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RH1020-CQ84V
RH1280-CQ172V
RH54SXxx-CQ256V
5962F90965
5962F92156
RT54SX16-CQ208
RT54SX16-CQ256
E1020
RH1280
RH1280
RT54SX72SCQ208
rt1280
RT54SX32S-CQ208
RTSX72
RT1020-CQ84B
aircraft logic gates
RTSX72S
RT1425
RT14100
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RT54SX32S-CQ208B
Abstract: RT54SX72SCQ208 RT1280A-CQ172 Actel A1020B RT54SX16S-CQ256B 30-80LET Single Event Latchup FPGA
Text: Actel FPGAs for Space Applications Uncompromising in the Extreme n n n n n Total Dose Capabilities from 5Krads to 1M rad Latch-up Immune Device Capacities from 4,000 to 72,000 Available Gates Highly Reliable, Non-Volatile Antifuse Technology Meets the Most Stringent Quality
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1-888-99-ACTEL
RT54SX32S-CQ208B
RT54SX72SCQ208
RT1280A-CQ172
Actel A1020B
RT54SX16S-CQ256B
30-80LET
Single Event Latchup FPGA
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ACTEL 1020B
Abstract: 1010B 40MX 42MX A54SX72A AC207 RT54SX72S RH1020 actel 1020 RT54SX-S
Text: Application Note AC207 Global Clock Networks in Actel Antifuse Devices System performance is one of the most important characteristics of a design. As a result, designers put a lot of effort into improving clock speed. Clock skew is often a limiting factor in attaining maximum
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AC207
ACTEL 1020B
1010B
40MX
42MX
A54SX72A
AC207
RT54SX72S
RH1020
actel 1020
RT54SX-S
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RTSX32
Abstract: RT54SX72S AC308 A42MX16 A54SX32A A54SX72A MX16 RTSX72-S Signal Path Designer
Text: Application Note AC308 Metastability Characterization Report for Actel Antifuse FPGAs Introduction Whenever asynchronous data is registered by a clocked flip-flop, there is a probability of setup or hold time violation on that flip-flop. In applications such as synchronization or data recovery, due to the
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AC308
RTSX32
RT54SX72S
AC308
A42MX16
A54SX32A
A54SX72A
MX16
RTSX72-S
Signal Path Designer
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ACTEL 1020B
Abstract: SIGNAL PATH designer actel 1020
Text: Application Note Global Clock Networks in Actel Antifuse Devices System performance is one of the most important characteristics of a design. As a result, designers put a lot of effort to improve clock speed. Clock skew is often a limiting factor in attaining maximum performance, forcing
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A1240XL
Abstract: a1240 Actel A1240 74LS A1020A A1400 ACTEL A1010A A1010a induced emf ACTEL A1240xl
Text: Appl i cat i o n N ot e Simultaneously Switching Output Limits for Actel FPGAs Introduction For high performance field programmable gate arrays FPGAs with many I/Os, the allowable number of Simultaneously Switching Outputs (SSOs) for each device is an important issue for system designers. The limits for SSOs
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A1010A/A1020A
A1010A/1020A
A1020A
A1280/A1280XL
A1240/A1240XL
A1240/A1225/A1225XL
A1225/A1225XL
A1400
A1240XL
a1240
Actel A1240
74LS
A1020A
ACTEL A1010A
A1010a
induced emf
ACTEL A1240xl
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actel a1240
Abstract: Ground bounce ACTEL A1010A Actel A1225 A1020A
Text: Appl i cat i on N ot e Simultaneously Switching Output Limits for Actel FPGAs Introduction For high performance field programmable gate arrays FPGAs with many I/Os, the allowable number of Simultaneously Switching Outputs (SSOs) for each device is an important issue for system designers. The limits for SSOs
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A1010A/A1020A
A1010A/1020A
A1020A
A1280/A1280XL
A1240/A1240XL
A1240/A1225/A1225XL
A1225/A1225XL
A1400
actel a1240
Ground bounce
ACTEL A1010A
Actel A1225
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RTSX32
Abstract: voter PAR64 REQ64 RT54SX72S RT54SX-S TM1019 Cqfp256
Text: Advanced v0.2 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 Additional SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate <
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RT54SX-S
100krad
RTSX32
voter
PAR64
REQ64
RT54SX72S
RT54SX-S
TM1019
Cqfp256
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RT54SX72S
Abstract: RT54SX-S voter PAR64 REQ64 TM1019 CQFP256
Text: Advanced v0.2 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 Additional SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate <
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RT54SX-S
100krad
RT54SX72S
RT54SX-S
voter
PAR64
REQ64
TM1019
CQFP256
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Pin Compatibility Allows Prototyping with Commercial SX-A FPGAs
Abstract: RT54SX72S-CQ256 RTSX32S
Text: Advanced v 0.1.1 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 Additional SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate <
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RT54SX-S
100krad
RT54SX-S
Pin Compatibility Allows Prototyping with Commercial SX-A FPGAs
RT54SX72S-CQ256
RTSX32S
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TM101
Abstract: No abstract text available
Text: Advanced v1.2.3 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate < 10–10
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RT54SX-S
100krad
RT54SX-S
TM1019
TM101
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Untitled
Abstract: No abstract text available
Text: Advanced v0.1.1 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 Additional SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate <
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RT54SX-S
100krad
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HiRel a54sx72a unused
Abstract: No abstract text available
Text: Advanced v1.5 RTSX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10
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TM1019
HiRel a54sx72a unused
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HiRel a54sx72a unused
Abstract: No abstract text available
Text: Advanced v1.3 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10
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RT54SX-S
RT54SX-S
TM1019
HiRel a54sx72a unused
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HiRel a54sx72a unused
Abstract: No abstract text available
Text: Advanced v1.6 RTSX-S RadTolerant FPGAs for Space Application S p ec i a l F e a tu r es fo r S p ac e • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10
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TM1019
HiRel a54sx72a unused
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A54SX72* radiation
Abstract: cg624 A54SX72A actel 1020 datasheet RT54SX72S RT54SX-S TM1019 HiRel a54sx72a unused
Text: Advanced v1.4 RT54SX-S RadTolerant FPGAs for Space Applications S p ec i a l F e a tu r es fo r S p ac e • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10
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RT54SX-S
TM1019
A54SX72* radiation
cg624
A54SX72A
actel 1020 datasheet
RT54SX72S
RT54SX-S
HiRel a54sx72a unused
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actel 1020
Abstract: actel 1020 datasheet RH1020 RT1020 schematic diagram 2 sc 1020
Text: Technical Brief Analysis of SDI/DCLK Issue for RH1020 and RT1020 B ac kg r o un d Fa i l u r e De sc r i p t i o n The SDI and DCLK pins pin numbers 61 and 62, respectively do not function properly when configured as outputs on all Actel RT1020 devices and older RH1020
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RH1020
RT1020
RT1020
RH1020
mid-1999
impRT1020
actel 1020
actel 1020 datasheet
schematic diagram 2 sc 1020
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Actel A1020
Abstract: A1020 Y A1010 A1020 A1020A C3254 CNT4A ACTEL A1010A A1010 actel DLM8
Text: ACTEL Æ CORP 34E § ACT 1 Field Programmable Gate Arrays c M 1 3 WÊ OiqgMqb ' 0000156 Ô 13ACT T—46—19—11 technology. The unique architecture offers gate array flexibility, high performance, and instant turnaround through user programming. Device utilization is typically 95% o f available logic
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A1010/A1010A:
A1020/A1020A:
GG00214
Actel A1020
A1020 Y
A1010
A1020
A1020A
C3254
CNT4A
ACTEL A1010A
A1010 actel
DLM8
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A1020A
Abstract: PH 84 CNT4A T-46 FADD32 ACTEL A1010A DLM8
Text: ACTEL CORP Æ te M 53E D • QnSMRf ci DDDD373 D23 *A C T ACT 1 Field Programmable Gate Arrays I Features Description • Up to 2000 Gate Array Gates 6000 PLD/LCA™ equivalent gates • Replaces up to 53 TTL Packages • Replaces up to 17 20-Pin PAL™ Packages
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0DQD373
20-Pin
A1010A
A1020A
Equiva005"
PH 84
CNT4A
T-46
FADD32
ACTEL A1010A
DLM8
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