1240XL
Abstract: ACTEL
Text: Errata Metastability Characterization Report Errata In Figure 2 on page 3 the X-axis and Y-axis are missing their designated names. Here is how the figure should appear. 30 25 ln MTBF (S 20 SX (0.35µm) RTSX32 (0.6µm) ACT3 (0.8µm) MX16 (0.45µm) 15 1240XL (0.6µm)
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5192670E-0/9
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rt54sx32su
Abstract: RTSX72 RTSX32SU RTSX72-S
Text: Advanced v0.1 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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rt54sx32su
RTSX72
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Pin Compatibility Allows Prototyping with Commercial SX-A FPGAs
Abstract: RT54SX72S-CQ256 RTSX32S
Text: Advanced v 0.1.1 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 Additional SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate <
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RT54SX-S
100krad
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Pin Compatibility Allows Prototyping with Commercial SX-A FPGAs
RT54SX72S-CQ256
RTSX32S
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Untitled
Abstract: No abstract text available
Text: v2 . 1 RTSX-S RadTolerant FPGAs Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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RTSX32su
Abstract: Actel a54sx72a tid Silicon Sculptor II
Text: v2.2 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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RTSX32su
Actel a54sx72a tid
Silicon Sculptor II
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RTSX32su
Abstract: RTSX32SU CQ84 RTSX72SU
Text: v2.0 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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RTSX32su
RTSX32SU CQ84
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Untitled
Abstract: No abstract text available
Text: Advanced v0.1.1 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 Additional SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate <
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RT54SX-S
100krad
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Abstract: No abstract text available
Text: v 2 .0 54SX Family FPGAs RadTolerant and HiRel Hig h D ens it y De vi ces Fe a t ur es • 16,000 and 32,000 Available Logic Gates Rad To ler ant 54S X Fam i ly • Tested Total Ionizing Dose TID Survivability Level • Up to 228 User I/Os • Radiation Performance to 100Krads (Si) (ICC Standby
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ESD-S3.1
Abstract: IC SEM 2005 RTSX32SU TM3015 TM3015.7 transistor N3B cmos esd sensitivity ionizer A54SX08A A54SX16A
Text: Application Note AC233 Electro-Static Discharge Introduction All electronic integrated circuit IC devices are susceptible to damage from static electricity or electrostatic discharge (ESD). While some devices can withstand thousands of volts of ESD before damage, others
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AC233
ESD-S3.1
IC SEM 2005
RTSX32SU
TM3015
TM3015.7
transistor N3B
cmos esd sensitivity
ionizer
A54SX08A
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RTSX32
Abstract: 54SX A54SX16 A54SX32 RT54SX RT54SX72S RTSX16
Text: v 2 .0 54SX Family FPGAs RadTolerant and HiRel Hig h D ens it y De vi ces Fe a t ur es • 16,000 and 32,000 Available Logic Gates Rad To ler ant 54S X Fam i ly • Tested Total Ionizing Dose TID Survivability Level • Up to 228 User I/Os • Radiation Performance to 100Krads (Si) (ICC Standby
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RTSX32
Abstract: voter PAR64 REQ64 RT54SX72S RT54SX-S TM1019 Cqfp256
Text: Advanced v0.2 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 Additional SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate <
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voter
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REQ64
RT54SX72S
RT54SX-S
TM1019
Cqfp256
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RTSX32SU
Abstract: RTSX32 PQFP die size C5249 bst r16 166 P790 actel 1020 datasheet A54SX72A CC256 CQ208
Text: Advanced v0.3 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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PQFP die size
C5249
bst r16 166
P790
actel 1020 datasheet
A54SX72A
CC256
CQ208
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RTSX72
Abstract: RTSX72SU A54SX72A TID "tristate buffer" A54SX32S-PQ208 RT54SXproto
Text: Advanced v0.2 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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"tristate buffer"
A54SX32S-PQ208
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RTSX32
Abstract: RT54SX32-CQ208 trd24 RTSX16 54SX A54SX16 A54SX32 RT54SX RT54SX72S Actel PQFP208
Text: v2.1 SX Family FPGAs RadTolerant and HiRel Features High Density Devices • • • RadTolerant SX Family • • • • • • Tested Total Ionizing Dose TID Survivability Level Radiation Performance to 100 Krads (Si) (ICC Standby Parametric) Devices Available from Tested Pedigreed Lots
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ACT1020
Abstract: JH05 MARKING CODE N-CHANNEL MOS FIELD EFFECT TRANSISTOR 44 pin actel 1020b JEDEC-A113 ACTEL 1020B ACP55 smd U1p Jl03 JL-03
Text: Quality & Reliability Guide February 2001 2001 Actel Corporation All Rights Reserved. Actel and the Actel logo are trademarks of Actel Corporation. All other brand or product names are the property of their respective owners. Contents 1. Overview of Actel’s Quality and Reliability Guide . . . . . . . . . . . . . . . . . . . .1
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RTSX32SU CQ84
Abstract: RT3PE3000L CQ256 CQFP 256 PIN actel A54SX32A SEU RT3PE600L Cqfp256 RTAX2000 ACTEL CCGA 624 mechanical rtax2000sl aircraft logic gates
Text: System-Critical FPGAs Product Catalog November 2009 Taking Designs from Earth to Outer Space Whether you’re designing for sea-level or 2,000,000 miles into space, Actel’s high-reliability, low-power FPGAs are your best choice. With a history of providing the most reliable, robust, low-power flash and antifuse-based FPGAs in
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Abstract: No abstract text available
Text: Preliminary v1.5 54SX Family FPGAs RadTolerant and HiRel Fe a t ur es • Up to 225 User I/Os Rad To ler ant 54S X Fam i ly • Up to 1,080 Dedicated Flip-Flops • Tested Total Ionizing Dose TID Survivability Level E asy L ogi c In teg ra ti on • Radiation Performance to 100Krads (Si) (ICC Standby
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RTSX32SU
Abstract: RTSX32SU CQ84 rtsx72su RTSX32 RTSX-SU 1/RTSX32su CC256 PRB-1 actel 1020 datasheet CG624
Text: Revision 7 RTSX-SU RadTolerant FPGAs UMC FuseLock Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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rtsx72su
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1/RTSX32su
CC256
PRB-1
actel 1020 datasheet
CG624
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RTSX32
Abstract: RT54SX72S AC308 A42MX16 A54SX32A A54SX72A MX16 RTSX72-S Signal Path Designer
Text: Application Note AC308 Metastability Characterization Report for Actel Antifuse FPGAs Introduction Whenever asynchronous data is registered by a clocked flip-flop, there is a probability of setup or hold time violation on that flip-flop. In applications such as synchronization or data recovery, due to the
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MX16
RTSX72-S
Signal Path Designer
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QFN108
Abstract: QFN-132 kl1-v1 208 pin rqfp drawing qfn132 RT3PE3000L CQ256 DIMENSIONS pqfp 100 actel package mechanical drawing Actel A40MX04 PBGA 23X23 0.8 pitch
Text: v 11. 2 Package Mechanical Drawings Ceramic Pin Grid Array 84-Pin CPGA Top View 0.050" ± 0.010" Pin #1 ID 0.045" 0.055" 0.015" 0.018" ± 0.002" 0.100" BSC 1.100" ± 0.020" square 0.072" 0.088" L 0.120" 0.140" Side View K J H G F 1.000" BSC E D C B A 1 2 3
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kl1-v1
208 pin rqfp drawing
qfn132
RT3PE3000L CQ256
DIMENSIONS pqfp 100
actel package mechanical drawing
Actel A40MX04
PBGA 23X23 0.8 pitch
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Actel APA075
Abstract: Core8051 SDLC TO SPI serial communication between 8051 16X50 serial communication in 8051 8051 using I2C BUS Development tools key board interface with 8051 8051 using I2C BUS APA075
Text: Platform8051 An Integrated Microprocessor Platform Key Features Platform8051 — A Modular 8-bit Microprocessor Platform Speeds System Design — Available as Individual Cores, as a Group or as a Complete Set — Supports Most Actel Device Families Core8051
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8051-Based
80C51/80C31/8051
ASM51)
Actel APA075
Core8051
SDLC TO SPI
serial communication between 8051
16X50
serial communication in 8051
8051 using I2C BUS Development tools
key board interface with 8051
8051 using I2C BUS
APA075
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RTSX32
Abstract: oscilloscope MTBF
Text: Application Note Metastability Characterization Report I n tro du ct i on The setup and hold times of a register may deviate from ideal register behavior in actual applications as a result of finite circuit delays. A synchronization failure may occur if the data and clock do not satisfy the setup- and hold-time
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sx08a
Abstract: RTSX16
Text: Application Note Hot-Swappable Capabilities of Actel’s SX-A and SX FPGAs Introduction Hot-Swappable-Tolerant Classification AA There is an increasing demand in the industry for systems to stay on-line during maintenance. System designers require devices to be operational when inserted or removed from
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Abstract: RTSX72SU AC251 RT54SX72S RT54SX-S in-rush RTSXSU ACTEL
Text: Application Note AC251 Power Cycling of RTSX-S Devices Introduction Power cycling may be defined in various terms, based on different applications. In this application note, power cycling refers to consecutive power-up/down sequences of array and I/O voltage supplies of RTSX-S
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RTSXSU ACTEL
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