U77-1163-2010P
Abstract: No abstract text available
Text: 8 7 4 5 6 3 2 1 REVISIONS REV DESC RIPTIO N DATE A PROPOSAL AUG06/09 B PLATING OPTION CONFIGURATION AUG17/09 SFP+ PRESS FIT CAGE P/N: U77-1163-2010P IF ORDERED SEPERATELY APPRD D D 16.26 15.01 SFP+ PRESS FIT CAGE (P/N: U77-A1639-X001 IF ORDERED SEPERATELY)
|
Original
|
PDF
|
AUG06/09
AUG17/09
U77-1163-2010P
U77-A1639-X001
JUL02/09
P-U77-C1619-X001
U77-1163-2010P
|
Untitled
Abstract: No abstract text available
Text: A B C D E G F H REVISIONS 5.00 [.197] DEEP THREADED HOLES SEE ORDERING CODE THREAD OPTION 2.50 .098 1 5.28 .208 REV DESCRIPTION, ECN, EAR NO. DATE APP'D F PRODUCT DRAWING EAR 14113 AUG23/12 K.L. G PRODUCT DRAWING (EAR 14292) AUG06/14 K.L. 1 ORDERING CODE: M U S B - E 1 5 1 - X X
|
Original
|
PDF
|
AUG23/12
AUG06/14
AUG31/06
P-MUSB-E151-XX
|
M/SMD w410
Abstract: No abstract text available
Text: 8 7 4 5 6 3 2 1 REVISIONS REV DESC RIPTIO N DATE A PROPOSAL AUG06/09 B PLATING OPTION CONFIGURATION AUG17/09 SFP+ PRESS FIT CAGE P/N: U77-1163-2010P IF ORDERED SEPERATELY APPRD D D 16.26 15.01 SFP+ PRESS FIT CAGE (P/N: U77-A1639-X001 IF ORDERED SEPERATELY)
|
Original
|
PDF
|
AUG06/09
AUG17/09
U77-1163-2010P
U77-A1639-X001
JUL02/09
P-U77-C1619-X001
M/SMD w410
|
P4C174
Abstract: No abstract text available
Text: P4C174 HIGH SPEED 8K x 8 CACHE TAG STATIC RAM FEATURES High Speed Address-To-Match - 8 ns Maximum Access Time Data Retention at 2V for Battery Backup Operation High-Speed Read-Access Time Advanced CMOS Technology – 8/10/12/15/20/25 ns Commercial – 15/20/25 ns (Military)
|
Original
|
PDF
|
P4C174
13-line
P4C174
iP4C174
SRAM118
SRAM118
Oct-05
Nov-05
|
cache tag Static RAM
Abstract: No abstract text available
Text: FT6175 High Speed 8K x 8 Cache Tag Static Ram FEATURES High Speed Address-To-Match - 8 ns Maximum Access Time Data Retention at 2V for Battery Backup Operation High-Speed Read-Access Time Advanced CMOS Technology – 8/10/12/15/20/25 ns Commercial – 15/20/25 ns (Military)
|
Original
|
PDF
|
FT6175
FT6175
Oct-05
Nov-05
Aug-06
SRAM118
cache tag Static RAM
|
Untitled
Abstract: No abstract text available
Text: P4C1026 ULTRA HIGH SPEED 256K x 4 STATIC CMOS RAM FEATURES Full CMOS, 6T Cell TTL/CMOS Compatible Outputs High Speed Equal Access and Cycle Times – 15/20/25/35 ns (Commercial/Industrial) – 20/25/35 ns (Military) Fully TTL Compatible Inputs Standard Pinout (JEDEC Approved)
|
Original
|
PDF
|
P4C1026
28-Pin
32-Pin
SRAM127
P4C1026
Oct-05
Aug-06
|
Untitled
Abstract: No abstract text available
Text: P4C1026 REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: SRAM127 P4C1026 ULTRA HIGH SPEED 256K x 4 STATIC CMOS RAM REV. ISSUE DATE ORIG. OF CHANGE OR Oct-05 JDB New Data Sheet A Aug-06 JDB Updated SOJ package information Document # SRAM127 REV A DESCRIPTION OF CHANGE
|
Original
|
PDF
|
P4C1026
Oct-05
Aug-06
SRAM127
P4C1026
SRAM127
|
Untitled
Abstract: No abstract text available
Text: P4C174 REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: SRAM118 P4C174 HIGH SPEED 8Kx8 CACHE TAG STATIC RAM REV. ISSUE DATE ORIG. OF CHANGE OR 1997 DAB New Data Sheet A Oct-05 JDB Change logo to Pyramid B Nov-05 JDB Corrected error in Selection Guide C Aug-06 JDB
|
Original
|
PDF
|
P4C174
Oct-05
Nov-05
Aug-06
SRAM118
P4C174
SRAM118
|
Untitled
Abstract: No abstract text available
Text: P4C164 REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: SRAM115 P4C164 ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAMS REV. ISSUE DATE ORIG. OF CHANGE OR 1997 DAB New Data Sheet A Oct-05 JDB Change logo to Pyramid B Jun-06 JDB Added 28-pin ceramic DIP C Aug-06 JDB Added Lead Free Designation
|
Original
|
PDF
|
P4C164
Oct-05
Jun-06
Aug-06
SRAM115
P4C164
28-pin
SRAM115
|
Untitled
Abstract: No abstract text available
Text: P4C1256 HIGH SPEED 32K x 8 STATIC CMOS RAM FEATURES Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Fast tOE Automatic Power Down Packages —28-Pin 300 mil DIP, SOJ, TSOP —28-Pin 300 mil Ceramic DIP —28-Pin 600 mil Ceramic DIP —28-Pin CERPACK
|
Original
|
PDF
|
P4C1256
--28-Pin
--32-Pin
144-bit
|
Untitled
Abstract: No abstract text available
Text: P4C1026 ULTRA HIGH SPEED 256K x 4 STATIC CMOS RAM FEATURES Full CMOS, 6T Cell TTL/CMOS Compatible Outputs High Speed Equal Access and Cycle Times – 15/20/25/35 ns (Commercial/Industrial) – 20/25/35 ns (Military) Fully TTL Compatible Inputs Standard Pinout (JEDEC Approved)
|
Original
|
PDF
|
P4C1026
28-Pin
32-Pin
P4C1026
SRAM127
SRAM127
|
BAS170W
Abstract: No abstract text available
Text: BAS170W 2 Silicon Schottky Diode 1 General-purpose diode for high-speed switching Circuit protection Voltage clamping High-level detection and mixing Type BAS170W Marking 7 VPS05176 Pin Configuration 1=C 2=A Package SOD323 - Maximum Ratings Parameter
|
Original
|
PDF
|
BAS170W
VPS05176
OD323
Aug-06-2001
EHB00042
BAS170W
|
Untitled
Abstract: No abstract text available
Text: P4C1256L LOW POWER 32K x 8 STATIC CMOS RAM FEATURES Common Data I/O Three-State Outputs Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Automatic Power Down Packages —28-Pin 600 mil DIP —28-Pin 300 mil CERDIP —28-Pin 330 mil Narrow SOP
|
Original
|
PDF
|
P4C1256L
70mA/85mA
--28-Pin
144-bit
32Kx8.
SRAM121
P4C1256L
|
BDP955
Abstract: BDP951 BDP952 BDP953 BDP956 VPS05163
Text: BDP951 . BDP955 NPN Silicon AF Power Transistor For AF driver and output stages 4 High collector current High current gain Low collector-emitter saturation voltage 3 Complementary types: BDP952 . BDP956 PNP 2 1 Type Marking Pin Configuration
|
Original
|
PDF
|
BDP951
BDP955
BDP952
BDP956
OT223
BDP953
VPS05163
BDP955
BDP951
BDP952
BDP953
BDP956
VPS05163
|
|
|
marking code p18
Abstract: AUG04A48 AUG06F48 AUG07G48 AUG08M48 AUG08Y48 CISPR22 GMA-10A
Text: Technical Reference Note Ultra Low Profile AUG 20W Series AUG 20W Ultra Low Profile DC – DC Module Pb-free reflow compatible and ROHS Compliant The AUG 20W series is Astec’s new Ultra Low Profile, 48Vin, SMT isolated single output modules. With the Ultra Low
|
Original
|
PDF
|
48Vin,
60Vdc
75Vdc
100degC
marking code p18
AUG04A48
AUG06F48
AUG07G48
AUG08M48
AUG08Y48
CISPR22
GMA-10A
|
P4C1026
Abstract: P4C1258
Text: P4C1026 ULTRA HIGH SPEED 256K x 4 STATIC CMOS RAM FEATURES Full CMOS, 6T Cell TTL/CMOS Compatible Outputs High Speed Equal Access and Cycle Times – 15/20/25/35 ns (Commercial/Industrial) – 20/25/35 ns (Military) Fully TTL Compatible Inputs Standard Pinout (JEDEC Approved)
|
Original
|
PDF
|
P4C1026
28-Pin
32-Pin
P4C1026
toler150
SRAM127
SRAM127
P4C1258
|
P4C163
Abstract: P4C163L
Text: P4C163/P4C163L ULTRA HIGH SPEED 8K x 9 STATIC CMOS RAMS FEATURES Data Retention with 2.0V Supply, 10 µA Typical Current P4C163L Military Common I/O Fully TTL Compatible Inputs and Outputs Standard Pinout (JEDEC Approved) – 28-Pin 300 mil DIP, SOJ – 28-Pin 350 x 550 mil LCC
|
Original
|
PDF
|
P4C163/P4C163L
P4C163L
28-Pin
25/35ns
25/35/45ns
P4C163
728-bit
|
P3C1256
Abstract: 1519B
Text: P3C1256 HIGH SPEED 32K x 8 3.3V STATIC CMOS RAM FEATURES 3.3V Power Supply Common Data I/O High Speed Equal Access and Cycle Times — 12/15/20/25 ns (Commercial) — 15/20/25 ns (Industrial) Three-State Outputs Low Power Advanced CMOS Technology Single 3.3 Volts ±0.3Volts Power Supply
|
Original
|
PDF
|
P3C1256
--28-Pin
P3C1256
144-bit
32Kx8.
SRAM122
SRAM122
Oct-05
1519B
|
100DM
Abstract: 1519B P4C164 P4C164L
Text: P4C164 ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAMS FEATURES Full CMOS, 6T Cell Common Data I/O High Speed Equal Access and Cycle Times – 8/10/12/15/20/25/35/70/100 ns (Commercial) – 10/12/15/20/25/35/70/100 ns(Industrial) – 12/15/20/25/35/45/70/100 ns (Military)
|
Original
|
PDF
|
P4C164
28-Pin
100ns)
32-Pin
100DM
1519B
P4C164
P4C164L
|
Untitled
Abstract: No abstract text available
Text: P4C164 ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAMS FEATURES Full CMOS, 6T Cell Common Data I/O High Speed Equal Access and Cycle Times – 8/10/12/15/20/25/35/70/100 ns (Commercial) – 10/12/15/20/25/35/70/100 ns(Industrial) – 12/15/20/25/35/45/70/100 ns (Military)
|
Original
|
PDF
|
P4C164
P4C164L
28-Pin
100ns)
|
Untitled
Abstract: No abstract text available
Text: P4C1981/1981L, P4C1982/1982L REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: SRAM114 P4C1981 / P4C198L, P4C1982 / P4C1982L ULTRA HIGH SPEED 16K x 4 STATIC CMOS RAMS REV. ISSUE DATE ORIG. OF CHANGE OR 1997 DAB New Data Sheet A Oct-05 JDB Change logo to Pyramid B
|
Original
|
PDF
|
P4C1981/1981L,
P4C1982/1982L
Oct-05
Aug-06
SRAM114
P4C1981
P4C198L,
P4C1982
P4C1982L
SRAM114
|
Untitled
Abstract: No abstract text available
Text: 3 4 THIS DRAWING IS UNPUBLISHED. COPYRIGHT RELEASED BY TYCO ELECTRONICS CORPORATION. FOR PUBLICATION - 2 - LOC ALL RIGHTS RESERVED. REVISIONS DIST GP 00 LTR DESCRIPTION A 4.06 — [. 1 6 0 ] TYP DATE DWN 2 1 AUG06 REVISED PER E C O -06- 000724 APVD JDP CWR
|
OCR Scan
|
PDF
|
AUG06
30APR04
31MAR2000
|
Untitled
Abstract: No abstract text available
Text: 4 TH IS DRAWING IS U N P U B LIS H E D . RELEASED FOR PUBLICATIO N ALL COPYRIGHT 2 3 RIGHTS - - LOC RESERVED. DIST EH BY TYCO ELECTRONICS CORPORATION. REVISIONS 00 LTR D E SC RIPTIO N DWN DATE APVD D1 ECO—0 6 —0 1 0 6 4 9 0 1 AUG06 JM c c D2 REV 11DCT06
|
OCR Scan
|
PDF
|
AUG06
11DCT06
|
Untitled
Abstract: No abstract text available
Text: THIS DRAWING IS UNPUBLISHED. COPYRIGHT - RELEASED FOR PUBLICATION BY TYCO ELECTRONICS CORPORATION. DIST LOC ALL RIGHTS RESERVED. REVISIONS J LTR B2 DESCRIPTION REDRAW W /0 CHANGE DWN DATE E C R -0 6 -0 1 8497 APVD MS KB 01AUG 06 6. 2 L ±0. 3 3. 6 l. 8 3.
|
OCR Scan
|
PDF
|
01AUG
17518G-1
01AUG06
AUG06
31MAR20Q0
\en32
|