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    Infineon Technologies AG CY8C4125AXI-483

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    DigiKey CY8C4125AXI-483 Tray 6,216 1
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    Infineon Technologies AG CY8C4245AXI-483

    IC MCU 32BIT 32KB FLASH 44TQFP
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    DigiKey CY8C4245AXI-483 Tray 2,626 1
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    Mouser Electronics CY8C4245AXI-483 4,326
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    Infineon Technologies AG CY8C4124AXI-443T

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    DigiKey CY8C4124AXI-443T Cut Tape 1,485 1
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    Mouser Electronics CY8C4124AXI-443T 1,500
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    Infineon Technologies AG CY8C4125AXI-483T

    IC MCU 32BIT 32KB FLASH 44TQFP
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    DigiKey CY8C4125AXI-483T Cut Tape 1,475 1
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    Infineon Technologies AG CY8C4245AXI-473

    IC MCU 32BIT 32KB FLASH 44TQFP
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    DigiKey CY8C4245AXI-473 Tray 1,154 1
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    AXI4 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    AMBA AXI4 verilog code

    Abstract: AMBA AXI specifications AMBA AXI4 pci to pci bridge verilog code Xilinx DS820 system verilog pcie microblaze state machine diagram for axi bridge Xilinx Virtex6 Design Kit 0X138
    Text: LogiCORE IP AXI EP Bridge for PCI Express v1.01.a DS820 October 19, 2011 Product Specification Introduction t LogiCORE IP Facts Table The Advanced eXtensible Interface (AXI) Endpoint (EP) Bridge for PCI Express is an interface between the AXI4 bus and PCI Express. Definitions and


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    DS820 64-bit 32-bitthe AMBA AXI4 verilog code AMBA AXI specifications AMBA AXI4 pci to pci bridge verilog code Xilinx DS820 system verilog pcie microblaze state machine diagram for axi bridge Xilinx Virtex6 Design Kit 0X138 PDF

    Untitled

    Abstract: No abstract text available
    Text: LogiCORE IP SPI-4.2 v13.0 DS823 March 20, 2013 Product Specification Introduction LogiCORE IP Facts Core Specifics Device Family 1 Kintex-7, Virtex-7 Supported User Interface AXI4-Lite and AXI4-Stream Resources Used (2) Alignment Type FPGAs The Xilinx SPI-4.2 (PL4) core implements and is


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    DS823 64-bit 128-bit PDF

    XC6LX240T-FF1156

    Abstract: virtex GTH AMBA AXI kintex 7 AMBA file write AXI verilog code aurora GTX virtex-7 XC6LX240T AMBA AXI4 verilog code 64B66B
    Text: LogiCORE IP Aurora 64B/66B v7.1 DS815 April 24, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP Aurora 64B/66B core supports the AMBA protocol AXI4-Stream user interface. It implements the Aurora 64B/66B protocol using the


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    64B/66B DS815 XC6LX240T-FF1156 virtex GTH AMBA AXI kintex 7 AMBA file write AXI verilog code aurora GTX virtex-7 XC6LX240T AMBA AXI4 verilog code 64B66B PDF

    SPARTAN-6 GTP

    Abstract: msi g31 axi wrapper state machine diagram for axi bridge programmed fpga diagram and state machine axi 3 protocol XC6SLX4 DS820 MSIE PCIE interface
    Text: LogiCORE IP AXI Bridge for PCI Express v1.03.a DS820 April 24, 2012 Product Specification Introduction t LogiCORE IP Facts Table The Advanced eXtensible Interface (AXI) Root Port/Endpoint (RP/EP) Bridge for PCI Express is an interface between the AXI4 and PCI Express.


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    DS820 SPARTAN-6 GTP msi g31 axi wrapper state machine diagram for axi bridge programmed fpga diagram and state machine axi 3 protocol XC6SLX4 MSIE PCIE interface PDF

    virtex-7

    Abstract: Aurora LX240T virtex7 vhdl coding for error correction and detection xilinx virtex-7 Spartan-6 LXT LX240T-FF1156 kintex 7
    Text: LogiCORE IP Aurora 8B/10B v8.1 DS797 April 24, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP Aurora 8B/10B core supports the AMBA protocol AXI4-Stream user interface. The core implements the Aurora 8B/10B protocol using the


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    8B/10B DS797 virtex-7 Aurora LX240T virtex7 vhdl coding for error correction and detection xilinx virtex-7 Spartan-6 LXT LX240T-FF1156 kintex 7 PDF

    g17g2

    Abstract: state machine axi 3 protocol state machine diagram for axi bridge state machine axi DS712 G17G-2 AMBA AXI specifications 17256 XILINX
    Text: LogiCORE IP AXI PLBv46 Bridge v2.02.a DS712 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Table The Advanced Microcontroller Bus Architecture (AMBA ) Advanced eXtensible Interface (AXI4) to Processor Local Bus (PLB v4.6) Bridge translates AXI


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    PLBv46 DS712 32/64-bit ZynqTM-7000 g17g2 state machine axi 3 protocol state machine diagram for axi bridge state machine axi G17G-2 AMBA AXI specifications 17256 XILINX PDF

    N25Q256

    Abstract: WINBOND W25Q80 XC7K325TFFG900 XC6VLX130TFF1156 W25Q64VSFIG XC7K325T W25Q64vs axi4 DS843 W25Q80
    Text: LogiCORE IP AXI Quad Serial Peripheral Interface AXI Quad SPI (v1.00a) DS843 October 19, 2011 Product Specification Introduction LogiCORE IP Facts The AXI Quad Serial Peripheral Interface connects the AXI4 interface to SPI slave devices that support the


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    DS843 M68HC11 N25Q256 WINBOND W25Q80 XC7K325TFFG900 XC6VLX130TFF1156 W25Q64VSFIG XC7K325T W25Q64vs axi4 W25Q80 PDF

    Untitled

    Abstract: No abstract text available
    Text: Video Broadcaster v1.00a DS880 October 16, 2012 Product Specification Introduction LogiCORE IP Facts Table The Xilinx LogiCORE IP Video Broadcaster core provides a flexible block for replicating a single inbound AXI4-Stream interface into multiple outbound


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    DS880 ZynqTM-7000 PDF

    XC7K325TFFG900

    Abstract: W25Q64VSFIG WINBOND W25Q80 SPARTAN 6 spi numonyx XPS ipic burst axi4 example Quad SPI N25Q256 NUMONYX xilinx spi XC7V285TFFG784-3 XC7K325T-ffg900
    Text: LogiCORE IP AXI Quad Serial Peripheral Interface AXI Quad SPI (v2.00a) DS843 July 25, 2012 Product Specification Introduction LogiCORE IP Facts The AXI Quad SPI connects the AXI4 interface to those SPI slave devices that support Standard, Dual or Quad


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    DS843 M68HC11 Zynq-7000 XC7K325TFFG900 W25Q64VSFIG WINBOND W25Q80 SPARTAN 6 spi numonyx XPS ipic burst axi4 example Quad SPI N25Q256 NUMONYX xilinx spi XC7V285TFFG784-3 XC7K325T-ffg900 PDF

    zynq axi ethernet software example

    Abstract: microblaze, SDK axi ethernet software example MM2S Xilinx ISE Design Suite 0x10111213 axi4
    Text: LogiCORE IP AXI4-Stream FIFO v2.01a DS806 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Table The AXI4-Stream FIFO core allows memory mapped access to a AXI4-Stream interface. The core can be used to interface to the AXI Ethernet without the complexity


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    DS806 ZynqTM-7000, zynq axi ethernet software example microblaze, SDK axi ethernet software example MM2S Xilinx ISE Design Suite 0x10111213 axi4 PDF

    xc6vlx130t-ff1156

    Abstract: XILINX ipic axi
    Text: LogiCORE IP AXI Serial Peripheral Interface AXI SPI (v1.02.a) DS742 January 18, 2012 Product Specification Introduction LogiCORE IP Facts The AXI Serial Peripheral Interface (SPI) connects to the Advanced eXtensible Interface (AXI4). This core provides a serial interface to SPI devices such as SPI


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    DS742 M68HC11 32-bit xc6vlx130t-ff1156 XILINX ipic axi PDF

    AMBA AXI4 stream specifications

    Abstract: state machine axi 3 protocol state machine axi Xilinx ISE Design Suite
    Text: LogiCORE IP AXI Slave Burst v1.00b DS769 October 16, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP AXI Slave Burst core provides an interface between the AXI4 memory-mapped interface and the IP interconnect interface. This core is designed


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    DS769 PLBv46 ZynqTM-7000 AMBA AXI4 stream specifications state machine axi 3 protocol state machine axi Xilinx ISE Design Suite PDF

    Untitled

    Abstract: No abstract text available
    Text: LogiCORE IP AXI Quad Serial Peripheral Interface AXI Quad SPI v2.00a DS843 December 18, 2012 Product Specification Introduction LogiCORE IP Facts The AXI Quad SPI connects the AXI4 interface to those SPI slave devices that support Standard, Dual or Quad


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    DS843 M68HC11 Zynq-7000 PDF

    XC6SLX45-2FGG484

    Abstract: SPARTAN 6 xc6slx45 SLV64 spartan-6 XC6SLX45 DS765 XILINX ipic kintex 7 XC7K410TFFG676-3
    Text: LogiCORE IP AXI4-Lite IPIF v1.01.a DS765 January 18, 2012 Product Specification Introduction LogiCORE IP Facts Table The AXI4-Lite IP Interface (IPIF) is a part of the Xilinx family of Advanced RISC Machine (ARM ) Advanced Microcontroller Bus Architecture (AMBA®) Advanced


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    DS765 ZynqTM-7000fy XC6SLX45-2FGG484 SPARTAN 6 xc6slx45 SLV64 spartan-6 XC6SLX45 XILINX ipic kintex 7 XC7K410TFFG676-3 PDF

    ch249

    Abstract: No abstract text available
    Text: LogiCORE IP SPI-4.2 v12.2 DS823 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Core Specifics Device Family 1 Kintex-7, Virtex-7 Supported User Interface AXI4-Lite and AXI4-Stream Resources Used (2) Alignment Type FPGAs The Xilinx SPI-4.2 (PL4) core implements and is


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    DS823 OIF-SPI4-02 64-bit 128-bit ch249 PDF

    Untitled

    Abstract: No abstract text available
    Text: 66AK2E05, 66AK2E02 SPRS865B—June 2013—Revised January 2014 Multicore DSP+ARM KeyStone II System-on-Chip SoC 1 66AK2E05/02 Features and Description • ARM Cortex -A15 MPCore™ CorePac – Up to Four ARM Cortex-A15 Processor Cores at up to 1.4-GHz


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    66AK2E05, 66AK2E02 SPRS865Bâ 66AK2E05/02 Cortex-A15 Cortex-A15 TMS320C66xâ PDF

    Untitled

    Abstract: No abstract text available
    Text: AM5K2E04, AM5K2E02 SPRS864B—June 2013—Revised January 2014 Multicore ARM KeyStone II System-on-Chip SoC 1 AM5K2E04/02 Features and Description • ARM Cortex -A15 MPCore™ CorePac – Up to Four ARM Cortex-A15 Processor Cores at up to 1.4-GHz – 4MB L2 Cache Memory Shared by all Cortex-A15


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    AM5K2E04, AM5K2E02 SPRS864Bâ AM5K2E04/02 Cortex-A15 Cortex-A15 PDF

    Untitled

    Abstract: No abstract text available
    Text: AM5K2E04, AM5K2E02 SPRS864B—June 2013—Revised January 2014 Multicore ARM KeyStone II System-on-Chip SoC 1 AM5K2E04/02 Features and Description • ARM Cortex -A15 MPCore™ CorePac – Up to Four ARM Cortex-A15 Processor Cores at up to 1.4-GHz – 4MB L2 Cache Memory Shared by all Cortex-A15


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    AM5K2E04, AM5K2E02 SPRS864Bâ AM5K2E04/02 Cortex-A15 Cortex-A15 PDF

    P281 B01

    Abstract: G187
    Text: LogiCORE IP Processing System 7 v4.02a DS871 October 16, 2012 Product Specification Introduction LogiCORE IP Facts Table The Processing System 7 IP is the software interface around the Zynq Processing System. The Zynq -7000 family consists of an system-on-chip (SoC) style


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    DS871 Zynq-7000 P281 B01 G187 PDF

    Untitled

    Abstract: No abstract text available
    Text: LogiCORE IP AXI Interconnect v1.06.a DS768 December 18, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP AXI Interconnect core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices. The AXI


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    DS768 PDF

    SPRS836D

    Abstract: No abstract text available
    Text: TCI6638K2K SPRS836D—February 2012—Revised October 2013 Multicore DSP+ARM KeyStone II System-on-Chip SoC 1 TCI6638K2K Features and Description 1.1 Features • Eight TMS320C66x DSP Core Subsystems (C66x CorePacs), Each With – 1.0 GHz or 1.2 GHz C66x Fixed/Floating-Point DSP Core


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    TCI6638K2K SPRS836Dâ TCI6638K2K TMS320C66xâ 1024K SPRS836D PDF

    Untitled

    Abstract: No abstract text available
    Text: AM5K2E04/02 Multicore ARM KeyStone II System-on-Chip SoC Data Manual PRODUCT PREVIEW information applies to products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products


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    AM5K2E04/02 SPRS864A SPRS864Aâ PDF

    AMBA AXI4 verilog code

    Abstract: ZYNQ-7000 BFM 20/ZYNQ-7000 BFM
    Text: LogiCORE IP AXI Bus Functional Models v3.00.a DS824 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Table The Xilinx LogiCORE IP AXI Bus Functional Models (BFMs), developed for Xilinx by Cadence Design Systems, support the simulation of


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    DS824 AMBA AXI4 verilog code ZYNQ-7000 BFM 20/ZYNQ-7000 BFM PDF

    XC7K325T-ffg900

    Abstract: XC7K325TFFG900 VX690T
    Text: Vivado Design Suite User Guide Release Notes, Installation, and Licensing UG973 v2013.2 June 19, 2013 Notice of Disclaimer The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum


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    UG973 v2013 UG900) XTP025) UG344) DS593) DS097) vivado2013-1 XC7K325T-ffg900 XC7K325TFFG900 VX690T PDF