Untitled
Abstract: No abstract text available
Text: M B86936 FUJITSU 930 SERIES 32-BIT RISC EMBEDDED PROCESSOR APRIL, 1996 • On-chip clock generator circuit FEATURES • JTAG test interface • 25 and 50 MHz versions • Emulator support hardware • Clock doubler for 50 MHz version • Single vector trapping
|
OCR Scan
|
PDF
|
B86936
32-BIT
256Mbyte
374175b
D01757A
|
Untitled
Abstract: No abstract text available
Text: C h a pt er E10 Floating-Point Unit E10.1 Overview of the B86936 Floating-Point Unit The B86936 FPU fully conforms to the A N SI/IEEE Standard 754-1985, the SPARC Architecture Version 8 specification, and he SPARC IEEE754 Implementation Recommendation except for the Nonstandard FP (NS=1 mode implementation.
|
OCR Scan
|
PDF
|
MB86936
IEEE754
|
MARKING cfk
Abstract: marking code CFK MB86936A
Text: B86936 FUJITSU 930 SERIES 32-BIT RISC EMBEDDED PROCESSOR AUGUST, 1996 • • • • JTAG test interface Emulator support hardware Single vector trapping Power down modes, with global or selective power down • 0.5 micron gate, 3 level metal CMOS technology,
|
OCR Scan
|
PDF
|
MB86936
32-BIT
256Mbyte
MARKING cfk
marking code CFK
MB86936A
|
Untitled
Abstract: No abstract text available
Text: MB86831 FUJITSU SPARCIiteCPU O cto b e r 1996 F unction S pe cifica tion ADVANTAGES — Burst Mode Support — 6 Programmable Chip Select Functions CPU Core Advantages — 6 Programmable Wait State Controls • IU Integer Unit — Supports 8/16-bit Bus — 66MHz/80MHz/100MHz* operation
|
OCR Scan
|
PDF
|
MB86831
8/16-bit
66MHz/80MHz/100MHz*
Window/136
32-bit
|
Untitled
Abstract: No abstract text available
Text: B86936 FUJITSU 930 SERIES 32-BIT RISC EMBEDDED PROCESSOR AUGUST, 1996 • JTAG test interface FEATURES • Emulator support hardware • 50 MHz version with clock doubling • • SPARC* high performance RISC architecture • High Performance SPARC FPU, ANSI/IEEE 754
|
OCR Scan
|
PDF
|
MB86936
32-BIT
B86936
B8693X
374T7Sb
4T75b
MB86936-25/50-PFV-G
|
Untitled
Abstract: No abstract text available
Text: C hapter E10 Floating-Point Unit E10.1 Overview of the B86936 Floating-Point Unit The B86936 FPU fully conforms to the ANSI/IEEE Standard 754-1985, the SPARC Architecture Version 8 specification, and the SPARC IEEE754 Implementation Recommendation except for the Nonstandard FP NS=1 mode implementation.
|
OCR Scan
|
PDF
|
MB86936
IEEE754
|
Untitled
Abstract: No abstract text available
Text: B86936 FUJITSU 930 SERIES 32-BIT RISC EMBEDDED PROCESSOR AD V A N C E D D A T A S H E E T JU N E 1995 • Interrupt Controller with fast interrupt response time, with programmable priority FEATURES • 2 24-bittim ersw ithl6-bitcounterand8-bitprescaler, with 3 modes o f operation
|
OCR Scan
|
PDF
|
MB86936
32-BIT
24-bittim
374T7Sb
MB86936-50-PFV-G
374R7St,
|
Untitled
Abstract: No abstract text available
Text: MB86935 FUJITSU 930 SERIES 32-BIT RISC EMBEDDED PROCESSOR November 1996 ADVANCE INFORMATION • Parity generation and checking FEATURES • • Programmable addressdecoderand wait-state genera tor 66MHz, 80MHz and 100 M H z versions each with clock doubling capability
|
OCR Scan
|
PDF
|
MB86935
32-BIT
66MHz,
80MHz
|