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    C502A Search Results

    C502A Result Highlights (2)

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    CLC502A/BPA Rochester Electronics LLC CLC502 - OP AMP, CLAMPING, LOW-GAIN, FAST-SETTLING - Dual marked (5962-9174301MPA) Visit Rochester Electronics LLC Buy
    CLC502AJE Rochester Electronics Operational Amplifier, 1 Func, 1600uV Offset-Max, PDSO8, PLASTIC, SOIC-8 Visit Rochester Electronics Buy
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    C502A Price and Stock

    Rochester Electronics LLC CLC502A-BPA

    IC OPAMP GP 1 CIRCUIT 8CDIP
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    DigiKey CLC502A-BPA Bulk 1,937 1
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    Rochester Electronics LLC CLC502AE-QML

    IC OPAMP GP 1 CIRCUIT 20LCCC
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    Analog Devices Inc DC502A

    BOARD EVAL FOR LT1767EMS8E
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    Bourns Inc 3549H-1AC-502A

    POT 5K OHM 2W HYBRITRON LINEAR
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    NIC Components Corp NANE46X14PJC2C502A0F

    Cellular - Bulk (Alt: NANE46X14PJC2C502A)
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    C502A Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: PLL620-80 Low Phase Noise XO 9.5-65MHz Output DIE CONFIGURATION FEATURES XIN OUTSEL0^ VDD VDD VDD VDD N/C Reserved OUTSEL1^ 24 23 22 21 20 19 18 17 26 Die ID: A2020-20B XOUT 27 N/C 28 S2^ 29 OE CTRL 30 N/C 31 C502A 16 CMOS 15 LVDSB 14 PECLB 13 12 VDDBUF


    Original     		PDF PLL620-80 5-65MHz A2020-20B C502A PLL620-80 19MHz 65MHz.

    5N521

    Abstract: No abstract text available
    Text: 1 PLL620-20 1 Low Phase Noise XO for HF Fund. and 3 rd O.T. DIE CONFIGURATION FEATURES XIN DESCRIPTION VDD VDD VDD N/C Reserved Reserved 25 24 23 22 21 20 19 18 26 Die ID: A1212-12 XOUT 27 N/C 28 N/C 29 OE CTRL 30 N/C 31 C502A 3 4 5 6 7 8 GND GND GND Reserved


    Original     		PDF PLL620-20 A1212-12 C502A A7F1B91 9E76B9A71/6* 7F1B91 B9D76 7761D EF946943F92 73456F 5N521

    A1010

    Abstract: C502A PLL620-00DC
    Text: PLL620-00 Low Phase Noise XO with multipliers for HF Fund. and 3 rd O.T. DIE SPECIFICATIONS 27 SEL3^ 28 SEL2^ 29 OE CTRL 30 NC 31 VDD SEL0^ SEL1^ OUTSEL1^ VDD XOUT VDD VDD 26 21 20 19 18 17 Die ID: A1010-10A C502A 3 4 5 6 7 8 GNDBUF (0,0) 2 GND Y X Name


    Original     		PDF PLL620-00 A1010-10A C502A PLL620-00 A1010 C502A PLL620-00DC

    oT 408

    Abstract: PL620-21
    Text: PL620-21 Low Phase Noise XO for HF Fund. and 3 rd O.T. DIE CONFIGURATION XIN VDD VDD VDD VDD DNC Reserved Reserved 24 23 22 21 20 19 18 XOUT 27 DNC 28 DNC 29 OE_CTRL 30 DNC 31 Die ID: A1919-19C C502A 3 4 5 6 GND Reserved X 7 8 GNDBUF 2 GNDBUF 1 GND (0,0)


    Original     		PDF PL620-21 100MHz 200MHz 200MHz A1919-19C PL620-21 oT 408

    a2020

    Abstract: C502A E5500 P620-80DC PLL620-80 PLL620-80DC
    Text: PLL620-80 Low Phase Noise XO 9.5-65MHz Output DIE CONFIGURATION FEATURES XIN OUTSEL0^ VDD VDD VDD VDD N/C Reserved OUTSEL1^ 24 23 22 21 20 19 18 17 26 Die ID: A2020-20B XOUT 27 N/C 28 S2^ 29 OE CTRL 30 N/C 31 C502A 16 CMOS 15 LVDSB 14 PECLB 13 12 VDDBUF


    Original     		PDF PLL620-80 5-65MHz A2020-20B C502A PLL620-80 19MHz 65MHz. a2020 C502A E5500 P620-80DC PLL620-80DC

    precision shunt regulators 431

    Abstract: TL4313 TL431A TL431B TL431C
    Text: CYStech Electronics Corp. Spec. No. : C502A3 Issued Date : 2003.03.26 Revised Date : 2007.12.21 Page No. : 1/6 Adjustable Precision Shunt Regulators TL431A3 Description TO-92 The TL431A3 series are three-terminal adjustable regulators with guaranteed thermal stability over applicable temperature ranges. The output voltage may be set to any


    Original     		PDF C502A3 TL431A3 TL431A3 50ppm/ UL94V-0 precision shunt regulators 431 TL4313 TL431A TL431B TL431C

    C502A

    Abstract: TL431A TL431B TL431C precision shunt regulators 431 Cystek
    Text: CYStech Electronics Corp. Spec. No. : C502A3 Issued Date : 2003.03.26 Revised Date : 2008.10.09 Page No. : 1/6 Adjustable Precision Shunt Regulators TL431A3 Description TO-92 The TL431A3 series are three-terminal adjustable regulators with guaranteed thermal stability over applicable temperature ranges. The output voltage may be set to any


    Original     		PDF C502A3 TL431A3 TL431A3 50ppm/ UL94V-0 C502A TL431A TL431B TL431C precision shunt regulators 431 Cystek

    precision shunt regulators 431

    Abstract: TL431XA3 TL431 TL431A TL431B TL431C
    Text: CYStech Electronics Corp. Spec. No. : C502A3 Issued Date : 2003.03.26 Revised Date : 2005.06.29 Page No. : 1/6 Adjustable Precision Shunt Regulators TL431XA3 Description The TL431 series are three-terminal adjustable regulators with guaranteed TO-92 thermal stability over applicable temperature ranges. The output voltage


    Original     		PDF C502A3 TL431XA3 TL431 50ppm/ UL94V-0 TL431A3 precision shunt regulators 431 TL431XA3 TL431A TL431B TL431C

    Untitled

    Abstract: No abstract text available
    Text: PL520-20 Low Phase Noise VCXO for 100-200MHz Fundamental Crystals DIE CONFIGURATION FEATURES XIN VDD VDD VDD VDD DNC DNC OUTSEL1 25 24 23 22 21 20 19 18 26 Die ID: A1919-19B XOUT 27 DNC 28 DNC 29 OE 30 VCON 31 DESCRIPTION C502A BLOCK DIAGRAM OE Q VCON Oscillator


    Original     		PDF PL520-20 100-200MHz 100MHz 200MHz 100MHz 200MHz 170MHz A1919-19B 14eserves

    Untitled

    Abstract: No abstract text available
    Text: PLL520-00 Low Phase Noise VCXO with multipliers for 100-200MHz Fund Xtal FEATURES OUTSEL0^ VDD VDD VDD VDD SEL0^ SEL1^ OUTSEL1^ 23 22 21 20 19 18 17 26 Die ID: A1919-19A XOUT 27 SEL3^ 28 SEL2^ 29 OE CTRL 30 VCON 31 C502A 16 CMOS 15 LVDSB 14 PECLB 13 12 VDDBUF


    Original     		PDF PLL520-00 100-200MHz A1919-19A C502A PLL520-00

    LM587

    Abstract: lm 587 C502A P580-30DC PL580-30 PL580-30DC
    Text: Preliminary 38MHz to 640MHz Low Phase Noise VCXO FEATURES OUTSEL0v VDDOSC VDDANA VDDANA VDDDIG SEL0^ SEL1^ OUTSEL1^ 23 22 21 20 19 18 XIN 26 XOUT 27 SEL2 28 DNC 29 Die ID: 2525-25 30 VCON 31 1 2 3 4 5 6 7 8 LP LM DNC DNC GNDDIG GNDBUF C502A (0,0) X The PL580-30 is a monolithic low jitter and low phase


    Original     		PDF 38MHz 640MHz C502A PL580-30 640MHz. LM587 lm 587 C502A P580-30DC PL580-30DC

    C502A

    Abstract: PLL620-20DC crystal ot 20 MHz
    Text: PLL620-20 Low Phase Noise XO for HF Fund. and 3 rd O.T. DIE CONFIGURATION FEATURES XIN 26 XOUT 27 N/C 28 N/C 29 OE CTRL 30 N/C 31 VDD N/C Reserved Reserved 23 VDD VDD 24 22 21 20 19 18 Die ID: A1212-12 C502A 3 4 5 6 7 8 GND GND Reserved GNDBUF GNDBUF (0,0)


    Original     		PDF PLL620-20 A1212-12 C502A PLL620-20 C502A PLL620-20DC crystal ot 20 MHz

    XTAL 25MHZ Datasheet

    Abstract: C502A P502-30DC PLL502-30 PLL502-30DC OSC 25MHz 3.3V a2828
    Text: 750kHz – 800MHz Low Phase Noise VCXO for 12 to 25MHz Crystals XIN 26 XOUT 27 SEL3^ 28 SEL2^ 29 OE_CTRL 30 VCON 31 VDD VDD VDD VDD SEL0^ SEL1^ OUTSEL1^ 24 23 22 21 20 19 18 Die ID: A2828-28 1 2 3 4 5 6 7 GND GND GND N/C GND C502A Note: ^ denotes internal pull up


    Original     		PDF 750kHz 800MHz 25MHz A2828-28 C502A PLL502-30 750kHz 12MHz XTAL 25MHZ Datasheet C502A P502-30DC PLL502-30DC OSC 25MHz 3.3V a2828

    454 marking CA 8

    Abstract: a2020 C502A P620-30DC PLL620-30 PLL620-30DC
    Text: PLL620-30 PECL and LVDS Low Phase Noise XO 32.5 to 130MHz output DIE CONFIGURATION FEATURES DIE SPECIFICATIONS XIN 26 XOUT 27 N/C 28 S2^ 29 OE CTRL 30 N/C 31 N/C Reserved Reserved 21 20 19 18 17 Die ID: A2020-20A C502A 5 GND 6 X 7 8 GNDBUF 4 GNDBUF 3 Reserved


    Original     		PDF PLL620-30 130MHz A2020-20A C502A 454 marking CA 8 a2020 C502A P620-30DC PLL620-30 PLL620-30DC

    C502A

    Abstract: PLL520-20 clock ma 1042
    Text: PLL520-20 Low Phase Noise VCXO for 100-200MHz Fundamental Crystals FEATURES DIE CONFIGURATION XIN VDD VDD VDD VDD DNC DNC OUTSEL1 (1550,1475) 25 24 23 22 21 20 19 18 17 26 Die ID: A1919-19B XOUT 27 DNC 28 DNC 29 OE 30 VCON 31 DESCRIPTION C502A BLOCK DIAGRAM


    Original     		PDF PLL520-20 100-200MHz A1919-19B 100MHz 200MHz 100MHz 200MHz 170MHz C502A PLL520-20 clock ma 1042

    Untitled

    Abstract: No abstract text available
    Text: PL520-00 Low Phase Noise VCXO with multipliers for 100 -200MHz Fund Xtal FEATURES OUTSEL0^ VDD VDD VDD VDD SEL0^ SEL1^ OUTSEL1^ 24 23 22 21 20 19 18 Die ID: A1919-19A XOUT 27 SEL3^ 28 SEL2^ 29 OE CTRL 30 VCON 31 C502A 17 GNDBUF 16 CMOS 15 LVDSB 14 PECLB


    Original     		PDF PL520-00 -200MHz 100MHz 200MHz 200MHz 400MHz 700MHz 800MHz

    a2020

    Abstract: No abstract text available
    Text: PL620-30 PECL and LVDS Low Phase Noise XO 32.5 to 130MHz output DIE CONFIGURATION FEATURES XIN DIE SPECIFICATIONS VDD VDD VDD VDD N/C Reserved Reserved 25 24 23 22 21 20 19 18 17 26 Die ID: A2020-20A XOUT 27 N/C 28 S2^ 29 OE CTRL 30 N/C 31 C502A Value Size


    Original     		PDF PL620-30 130MHz 65MHz 130MHz A2020-20A PL620-30 a2020

    C502A

    Abstract: PLL620-20DC
    Text: PLL620-20 Low Phase Noise XO for HF Fund. and 3 rd O.T. DIE CONFIGURATION FEATURES XIN VDD VDD VDD N/C Reserved Reserved 24 23 22 21 20 19 18 26 Die ID: A1212-12 XOUT 27 N/C 28 N/C 29 OE CTRL 30 N/C 31 C502A 3 4 5 6 7 8 GND GND Reserved GNDBUF GNDBUF (0,0)


    Original     		PDF PLL620-20 A1212-12 C502A PLL620-20 C502A PLL620-20DC

    clock ma 1042

    Abstract: C502A PLL620-20DC P620
    Text: PLL620-20 Low Phase Noise XO for HF Fund. and 3 rd O.T. FEATURES DIE CONFIGURATION 65 mil XIN VDD VDD VDD VDD N/C Reserved Reserved 24 23 22 21 20 19 18 26 Die ID: A1212-12 XOUT 27 N/C 28 N/C 29 OE CTRL 30 N/C 31 C502A 3 4 5 6 7 8 GND GND Reserved GNDBUF


    Original     		PDF PLL620-20 A1212-12 C502A PLL620-20 clock ma 1042 C502A PLL620-20DC P620

    P620-21DC

    Abstract: C502A PLL620-21 PLL620-21DC
    Text: PLL620-21 Low Phase Noise XO for HF Fund. and 3 rd O.T. VDD VDD VDD VDD DNC Reserved Reserved 24 23 22 21 20 19 18 26 XIN XOUT 27 DNC 28 DNC 29 OE_CTRL 30 DNC 31 Die ID: A1919-19C C502A 3 4 5 6 GND Reserved X 7 8 GNDBUF 2 GNDBUF 1 GND (0,0) Y (1550,1475)


    Original     		PDF PLL620-21 A1919-19C C502A PLL620-21 P620-21DC C502A PLL620-21DC

    a2020

    Abstract: clock ma 1042 C502A P620-30DC PLL620-30 PLL620-30DC
    Text: PLL620-30 PECL and LVDS Low Phase Noise XO 32.5 to 130MHz output DIE CONFIGURATION FEATURES XIN DIE SPECIFICATIONS VDD VDD VDD VDD N/C Reserved Reserved 25 24 23 22 21 20 19 18 17 26 Die ID: A2020-20A XOUT 27 N/C 28 S2^ 29 OE CTRL 30 N/C 31 C502A 5 Value


    Original     		PDF PLL620-30 130MHz C502A a2020 clock ma 1042 C502A P620-30DC PLL620-30 PLL620-30DC

    Untitled

    Abstract: No abstract text available
    Text: PL620-30 PECL and LVDS Low Phase Noise XO 32.5 to 130MHz output DIE CONFIGURATION FEATURES XIN DIE SPECIFICATIONS VDD VDD VDD VDD N/C Reserved Reserved 25 24 23 22 21 20 19 18 17 26 Die ID: A2020-20A XOUT 27 N/C 28 S2^ 29 OE CTRL 30 N/C 31 C502A Value Size


    Original     		PDF PL620-30 130MHz C502ght

    C502A

    Abstract: PLL520-20 VARICAPS
    Text: PLL520-20 Preliminary Low Phase Noise VCXO for 100-200MHz Fundamental Crystals FEATURES DIE CONFIGURATION 62 mil XIN VDD VDD VDD N/C DNC DNC 23 22 21 20 19 18 17 XOUT 27 DNC 28 DNC 29 OE CTRL 30 VCON 31 Die ID: A1919-19B C502A 4 5 6 GND Reserved X 7 8 GNDBUF


    Original     		PDF PLL520-20 100-200MHz A1919-19B C502A C502A PLL520-20 VARICAPS

    Untitled

    Abstract: No abstract text available
    Text: PLL520-80 Low Phase Noise VCXO 9.5-65MHz DIE CONFIGURATION FEATURES XIN DIE SPECIFICATIONS Name Value Size Reverse side Pad dimensions Thickness 62 x 65 mil GND 80 micron x 80 micron 10 mil OUTSEL0^ VDD VDD VDD VDD N/C Reserved OUTSEL1^ 24 23 22 21 20 19


    Original     		PDF PLL520-80 5-65MHz) C502A