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    Part ECAD Model Manufacturer Description Download Buy
    7MP6121SA33M Renesas Electronics Corporation 128KB CACHE MODULE Visit Renesas Electronics Corporation
    7MPV6186S15M Renesas Electronics Corporation 256KB ASYNC CACHE MODULE Visit Renesas Electronics Corporation
    7MP6122SA33M Renesas Electronics Corporation 256KB CACHE MODULE Visit Renesas Electronics Corporation
    7MP6076S15M Renesas Electronics Corporation 512KB ASYNC CACHE-APPLE Visit Renesas Electronics Corporation
    7MPV6122SA33M Renesas Electronics Corporation 256KB CACHE MODULE Visit Renesas Electronics Corporation
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    Advantech Co Ltd 96RC-CACHE-V-LS

    CACHE VAULT FLASH LSI LSICVM01
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    Advantech Co Ltd 96RC-CACHE-V-LS1

    CACHE VAULT FLASH LSI LSICVM01
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    Broadcom Limited MR CACHECADE OCS

    MegaRAID CacheCade Software License (Alt: MR CACHECADE OCS)
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    Mouser Electronics MR CACHECADE OCS
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    Chelsio Communications CACHE-4U-5

    5 TB, 4U, 10X1/10GBE SFP+, 2X100/1GBE BASE-T, 2.5M IOPS, SLC - Bulk (Alt: CACHE-4U-5)
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    HARTING Technology Group 09068009951

    DIN 41612 Connectors DIN PWR BLANK PIECE D20
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    TTI 09068009951 Bulk 17 3
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    CACHE Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    CQFP352

    Abstract: QFP352 MCGA349 MCGA-349 adc controller vhdl code atmel 268 AT7913 CQFP352 package vhdl code 64 bit FPU SPARC v8 architecture BLOCK DIAGRAM
    Text: ATMEL AT7913E SpaceWire Remote Terminal Controller RTC DATASHEET Features • LEON2-FT Sparc V8 Processor • • • • • • • • • • • 5 stage pipeline 4K instruction caches / 4K data caches Meiko FPU Interrupt Controller Uart serial links


    Original     		PDF AT7913E 32-bit 8bit/16bit 200Mbit/s CQFP352 QFP352 MCGA349 MCGA-349 adc controller vhdl code atmel 268 AT7913 CQFP352 package vhdl code 64 bit FPU SPARC v8 architecture BLOCK DIAGRAM

    EMIFA OMAP

    Abstract: GP011 EMIFA L138-FX-236-RC GP010 L138-DX-225-RI 512MB omapl138 Using the TMS320C674x BootLoader DDR2 ram model
    Text: Critical Link, LLC www.CriticalLink.com www.MityDSP.com MityDSP MityDSP-L138 Processor Card 12-JUL-2011 FEATURES • TI OMAP-L138 Dual Core Application Processor • • • • • - 456 MHz Max C674x VLIW DSP Floating Point DSP 32 KB L1 Program Cache 32 KB L1 Data Cache


    Original     		PDF MityDSP-L138 12-JUL-2011 OMAP-L138 C674x ARM926EJ-S 31-DEC-2010 EMIFA OMAP GP011 EMIFA L138-FX-236-RC GP010 L138-DX-225-RI 512MB omapl138 Using the TMS320C674x BootLoader DDR2 ram model

    atmel 324

    Abstract: ARM926EJ-S AT91SAM ISO7816 SAM9G45 AT91SAM9G45B-CU UHP4 ddr2 16bit NAND Flash controller ecc DFSDM
    Text: Features • 400 MHz ARM926EJ-S ARM Thumb® Processor – 32 KBytes Data Cache, 32 KBytes Instruction Cache, MMU • Memories • • • • – DDR2 Controller 4-bank DDR2/LPDDR, SDRAM/LPSDR – External Bus Interface supporting 4-bank DDR2/LPDDR, SDRAM/LPSDR, Static


    Original     		PDF ARM926EJ-STM 64-KByte 6438FS 19-Apr-11 atmel 324 ARM926EJ-S AT91SAM ISO7816 SAM9G45 AT91SAM9G45B-CU UHP4 ddr2 16bit NAND Flash controller ecc DFSDM

    TMS320C62x fft benchmark

    Abstract: TMS320C64xTM c6000 TMS320C6000TM TMS320C64X AC97 C6201 TMS320C6000 galois Architecture of TMS320C64X GSM Viterbi
    Text: T W H E O R L D L E A D E R I N D S P A N D A N A L O G Key Features • The world’s highest performance DSP core, scalable to 1.1 GHz and beyond. • New two-level cache supports the high-performance C64x DSP core. • Enhanced Direct Memory Access DMA provides more


    Original     		PDF C64xTM TMS320C6000TM TMS320C64x TMS320C64xTM com/sc/c64xupdate TMS320C64x, TMS320, TMS320C6000, TMS320C62x, C6000, TMS320C62x fft benchmark c6000 AC97 C6201 TMS320C6000 galois Architecture of TMS320C64X GSM Viterbi

    diode sy 710

    Abstract: YMB 24 H 04 D 35 sy 164 16-BYTE 80386DXRP 80386DXRP-16 80386DXRP-20 3BS16 T2716
    Text: 80386DXRP SPACE PRODUCTS GROUP SE22V10B SEGMENTATION UNIT EFFECTIVE ADDRESS BUS PAGING UNIT 3-INPUT ADDER BUS CONTROL 34 PAGE CACHE LIMIT AND ATTRIBUTE PLA BUS PROTECTION TEST UNIT CONTROL AND ATTRIBUTE PLA INTERNAL CONTROL BUS BARREL SHIFTER, ADDER DECODE AND


    Original     		PDF 80386DXRP SE22V10B 32-BIT 98Rev0 Q164-01 diode sy 710 YMB 24 H 04 D 35 sy 164 16-BYTE 80386DXRP 80386DXRP-16 80386DXRP-20 3BS16 T2716

    AM29030

    Abstract: MiniMON29K CERQUAD AM29035 CGY145 GQD144 ID31 Am29202 am29000 AM29030-25GC
    Text: AMENDMENT Am29030 and Am29035  RISC Microprocessors with 8-Kbyte/4-Kbyte Instruction Cache Advanced Micro Devices This amendment adds preliminary information on switching characteristics over commercial operating ranges for the 25-MHz Am29030 microprocessor.


    Original     		PDF Am29030TM Am29035 25-MHz AM29030 144-Lead GQD144) 145-Lead Am29000 Am29030 MiniMON29K CERQUAD CGY145 GQD144 ID31 Am29202 AM29030-25GC

    SCANBE

    Abstract: SCANBE ejector scanbe handle SCANBE connector mk48t59 MVME2304-0133 MVME2300 PMCSPAN-002 VME COnnector MPC604
    Text: MVME2300 TM VME Processor Modules ♦ PowerPC 603 or PowerPC 604™ 32-bit microprocessor ♦ L1 cache–16KB/16KB PowerPC 603 or 32KB/32KB PowerPC 604 ♦ 16MB to 128MB of on-board ECC DRAM ♦ Up to 1MB socketed Flash for on-board firmware or user-specified requirements


    Original     		PDF MVME2300 603TM 604TM 32-bit 16KB/16KB 32KB/32KB 128MB 32/64-bit 64-bit 32-bit SCANBE SCANBE ejector scanbe handle SCANBE connector mk48t59 MVME2304-0133 MVME2300 PMCSPAN-002 VME COnnector MPC604

    CBGA 255 motorola

    Abstract: MPC740 MPC7400 MPC7410 MPC745 MPC750 MPC755 MPC8240 MPC8245
    Text: Motorola PowerPC CPU Summary revised 02/19/2001 NickSaid 603e Code Name Motorola Names 100-133 MHz 200-300 MHz Stretch GoldenEye 603ePID6 100 MHz Internal 133 MHz x1.5, x2, x2.5, x3, x3.5, x4 Bus Interface Instructions per Clock L1 Cache Backside L2 Cache Support


    Original     		PDF 603ePID6 603ePID7t, MPC8240 MPC8245 64-bit CBGA 255 motorola MPC740 MPC7400 MPC7410 MPC745 MPC750 MPC755 MPC8240 MPC8245

    CY7C1339

    Abstract: No abstract text available
    Text: fax id: 1109 PRELIMINARY CY7C1339 128K x 32 Synchronous-Pipelined Cache RAM Features Functional Description • Low 1.65 mW standby power (f=0, L version) The CY7C1339 is a 3.3V 128K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary


    Original     		PDF CY7C1339 CY7C1339 100-MHz 166-MHz

    MVME5110

    Abstract: MVME51105E-2263 MVME5100 MVME51105E-2161 MVME51105E-2163 MVME5107-2163 MVME51105E-2261 IPMC7616E-002 MVME51005E-0161 SCANBE ejector
    Text: D ATA S H E E T MPC7410, MPC750 or MPC755 microprocessor with 32KB/32KB L1 cache Up to 2MB of secondary backside cache 100 MHz frontside bus Up to 512MB of on-board ECC SDRAM – expandable up to 1GB with optional RAM500 memory expansion modules 17MB flash memory


    Original     		PDF MPC7410, MPC750 MPC755 32KB/32KB 512MB RAM500 P1386 32/64-bit MVME5100 264MB/s MVME5110 MVME51105E-2263 MVME51105E-2161 MVME51105E-2163 MVME5107-2163 MVME51105E-2261 IPMC7616E-002 MVME51005E-0161 SCANBE ejector

    UltraSPARC-IIIi

    Abstract: NVRAM for Sun UltraSparc IIi UltraSPARC-III STP2003QFP 4900 H02 gigabyte MOTHERBOARD CIRCUIT diagram A27 639 SME2411 SME1430LGA-360 SME1430LGA-440
    Text: SME1430LGA-360 SME1430LGA-440 SME1430LGA-480 May 1999 UltraSPARC -IIi CPU DATA SHEET Highly Integrated 64-Bit RISC; L2-Cache, DRAM, PCI Interfaces DESCRIPTION The SME1430LGA CPU UltraSPARC-IIi microprocessor is a highly-integrated, 64-bit, SPARC V9 superscalar


    Original     		PDF SME1430LGA-360 SME1430LGA-440 SME1430LGA-480 64-Bit SME1430LGA 64-bit, SME1040 SME2411) UltraSPARC-IIIi NVRAM for Sun UltraSparc IIi UltraSPARC-III STP2003QFP 4900 H02 gigabyte MOTHERBOARD CIRCUIT diagram A27 639 SME2411 SME1430LGA-360 SME1430LGA-440

    tmp95fy64

    Abstract: TMP95FY64F tmp95fy CT 55H TLCS-90 LFFP100-P-1414-0 95fy64 QFP100P
    Text: CMOS 16-bit Microcontroller TMP95FY64F Page 1 of 92 This is the html version of the file . G o o g l e automatically generates html versions of documents as we crawl the web. To link to or bookmark this page, use the following url:


    Original     		PDF 16-bit TMP95FY64F pl/dane/uklady-scalone/Tmp95fy64f pl/dane/ukladyscalone/Tmp95fy64f TMP95FY64 TMP95FY64 TMP95FY64F tmp95fy CT 55H TLCS-90 LFFP100-P-1414-0 95fy64 QFP100P

    64KX32

    Abstract: 7C13 CY7C1329
    Text: fax id: 1080 1CY 7C13 29 CY7C1329 PRELIMINARY 64K x 32 Synchronous-Pipelined Cache RAM Features Functional Description • Low 1.65 mW standby power (f=0, L version) The CY7C1329 is 3.3V 64K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary


    Original     		PDF CY7C1329 CY7C1329 100-MHz 64KX32 7C13

    80486 microprocessor block diagram and pin diagram

    Abstract: 64KX32 CY7C1336
    Text: 36 PRELIMINARY CY7C1336 64K x 32 Synchronous Flow-Through 3.3V Cache RAM Features Functional Description • Supports 66-MHz microprocessor cache systems with zero wait states • 64K by 32 common I/O • Low Standby Power 1.65 mW, L version • Fast clock-to-output times


    Original     		PDF CY7C1336 66-MHz 117-MHz 100-pin CY7C1336 80486 microprocessor block diagram and pin diagram 64KX32

    Untitled

    Abstract: No abstract text available
    Text: TOSHIBA TC55V2325FF-100 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 65,536 W O R D x 32 BIT Synchronous Pipelined Burst SRAM DESCRIPTION The TC55V2325FF is a 2 ,0 9 7 ,1 5 2 bit synchronous pipelined burst SRAM that is organized as 65,536 words by 32 bits and designed for use in a secondary cache to support MPUs which have burst


    OCR Scan     		PDF TC55V2325FF-100 TC55V2325FF 64KX32 LQFP100-P-1420-0

    i486

    Abstract: No abstract text available
    Text: SN74BCT2141 2-WAY 8K x 18 SYNCHRONOUS CACHE DATA RAM D3613. A UG UST 1990 2-Way 8K x 18 Bit Architecture FN PACKAGE TOP VIEW Synchronous Read and Write Access at 50 MHz Clock Frequency Incorporates Burst Counter for Burst-Read (Read-Hit) Cycles or Burst-Write (Line-Fill)


    OCR Scan     		PDF SN74BCT2141 D3613. I486TM DQ13s BCT2141 i4861 i486

    D425G

    Abstract: ACT21 SN74BCT2166
    Text: SN74BCT2163, SN74BCT2164, SN74BCT2166 16K x 5 CACHE ADDRESS COMPARATORS/TAG RAMs SCHS012-D3513, JUNE 1990-REVISED NOVEMBER 1991 SN74BCT2163, SN74BCT2164 Fast Address to MATCH Delay. 12 ns Max FM PACKAGE CTOP VIEW ’BCT2163 Has Totem-Pole Match Output Q\*~


    OCR Scan     		PDF SN74BCT2163, SN74BCT2164, SN74BCT2166 SCHS012-D3513, 1990-REVISED BCT2163 BCT2164 BCT2166 D425G ACT21

    D2911

    Abstract: bit-slice
    Text: TMS2150A 512 x 8 CACHE ADDRESS COMPARATOR D2911, M A RCH 1 982-R E V IS E D SEP TE M B E R 1990 DW, JD, OR NT PACKAGE TOP VIEW ’ACT2150A is Recommended for New Designs RESET[ 1 U Fast Address to Match Valid Delay - Two Speed Ranges: 35 ns and 45 ns 512


    OCR Scan     		PDF TMS2150A D2911, 982-R ACT2150A 300-Mil 24-Pin D2911 bit-slice

    TC55188

    Abstract: TC55188T-25 TC55188T-20 TC55188T
    Text: •»ilK 2 - W A Y 4,096 W ORDS x 18 BITS/8,192 WORDS x 18 BITS CMOS STATIC CACHE DATA RAM DESCRIPTION The TC55188T is a 147,456bits high-speed static RAM which can be user-configured either a s 2-way 4,096 words by 18 bits or as 8,192 words by 18 bits. It is provided with a byte control, on-chip


    OCR Scan     		PDF TC55188T 456bits TC55188T--20, TC55188T-25, 55188T-30 TC55188 TC55188T-25 TC55188T-20

    AX2022

    Abstract: TACT2150 D6142
    Text: TACT2150 512 X 8 CACHE ADDRESS COMPARATOR D 2 9 9 3 . JA N U A R Y 1 9 8 7 - R E V IS E D SEPTEM BER 1967 Address to MATCH Valid Time TACT2150-20 . . . 20 ns max TACT2150-30 . . . 30 ns max DW, JD . OR NT PACKAGE 300-Mil 24-Pin Ceramic Side-Brazed or Plastic Dual-In-Line or Small Outline


    OCR Scan     		PDF TACT2150 300-Mil 24-Pin AX2022 D6142

    SCAD002

    Abstract: BCT2164
    Text: SN74BCT2163, SN74BCT2164, SN74BCT2166 16K x 5 CACHE ADDRESS COMPARATORS/TAG RAMs _ D3513, JUNE 1990 — REVISED A U G U S T 1990 • Fast Address to MATCH Delay . . .12-ns Max • ’BCT2163 has Totem-Pole Match Output


    OCR Scan     		PDF SN74BCT2163, SN74BCT2164, SN74BCT2166 D3513, 12-ns BCT2163 BCT2164 BCT2166 75-pF SCAD002

    Untitled

    Abstract: No abstract text available
    Text: SN74BCT2160 8K X 4 2-WAY CACHE ADDRESS COWIPARATOR/DATA RAM D 3512, JU NE 1990 FM PACKAGE TOP VIEW LO ^ n w r o < < < < < < Fast Address to Match Time . . . 12 ns Max 2-Way Architecture Significantly Improves Hit Rate 4 * Implements LRU Replacement Algorithm


    OCR Scan     		PDF SN74BCT2160 T2160

    um61168

    Abstract: No abstract text available
    Text: L I8 V 1 C U M 6 1 1 6 8 Series 2 x 4K x 16 CMOS CACHE RAM P R ELIM IN AR Y Features • S ingle + 5 V p o w e r su pp ly ■ ■ Access tim e s: 2 5 /3 5 /4 5 ns m ax. ■ ■ S u p p o rts h ig h speed 8 0 3 8 6 (3 3 /2 5 /2 0 M H z) w it h fa st ■ C u rre n t:


    OCR Scan     		PDF 52LPLC um61168

    Untitled

    Abstract: No abstract text available
    Text: SN74ACT2158, SN74ACT2159 8K x 9 CACHE ADDRESS COMPARATORS/DATA RAMs D 3 2 8 1 , M A Y 1 9 9 0 R E V IS E D J U N E 1990 Fast Address to MATCH Delay 22 ns Max FN PACKAGE TOP VIEW 8K x 10 Internal Static RAM ISCI 5 Ä • Word Reset Function for Single Entry


    OCR Scan     		PDF SN74ACT2158, SN74ACT2159 ACT2159) ACT2158)