CLOCK MANAGEMENT Search Results

CLOCK MANAGEMENT Result Highlights (5)

Part	Manufacturer	Description
TB67S539FTG	Toshiba Electronic Devices & Storage Corporation	Stepping Motor Driver/Bipolar Type/Vout(V)=40/Iout(A)=2/Clock Interface
TB67S149AFTG	Toshiba Electronic Devices & Storage Corporation	Stepping Motor Driver/Unipolar Type/Vout(V)=84/Iout(A)=3/Clock Interface
TB67S549FTG	Toshiba Electronic Devices & Storage Corporation	Stepping Motor Driver/Bipolar Type/Vout(V)=40/Iout(A)=1.5/Clock Interface
TB67S589FTG	Toshiba Electronic Devices & Storage Corporation	Stepping Motor Driver / Bipolar Type / Vout(V)=50 / Iout(A)=3.0 / CLK input type / VQFN32
TB67S589FNG	Toshiba Electronic Devices & Storage Corporation	Stepping Motor Driver / Bipolar Type / Vout(V)=50 / Iout(A)=3.0 / CLK input type / HTSSOP28

CLOCK MANAGEMENT Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
49fct3805a Abstract: 40 MHZ OSCILLATOR 49FCT805CT 5v927 74FCT88915TT70 74FCT3807D oscillator 2.048 mhz 5T9306 49FCT805BT 32 MHZ OSCILLATOR Text: IDT Clock Management PRODUCT FAMILY and the new LVDS clock fanout family, as well as the IDT Precision and Stratum WAN PLL clock generators. Advanced Clock Management — On Time, All the Time The IDT comprehensive portfolio of Clock Management products enhances time to	Original	1-04/EM/LMN/HOP/5K FLYR-TIME-00014 49fct3805a 40 MHZ OSCILLATOR 49FCT805CT 5v927 74FCT88915TT70 74FCT3807D oscillator 2.048 mhz 5T9306 49FCT805BT 32 MHZ OSCILLATOR	PDF
linear handbook Abstract: SSTL-18 AGX52005-1 Text: Section II. Clock Management This section provides information on clock management in Arria GX devices. It describes the enhanced and fast phase-locked loops PLLs that support clock management and synthesis for on-chip clock management, external system clock management, and high-speed I/O interfaces.	Original		PDF
EP1S60 Abstract: SPREAD-SPECTRUM SYSTEM Text: Section II. Clock Management This section provides information on clock management in Stratix GX devices. It describes the enhanced and fast phase-locked loops PLLs that support clock management and synthesis for on-chip clock management, external system clock management, and high-speed I/O interfaces.	Original		PDF
automatic change over switch circuit diagram Abstract: EP2S15 EP2S180 EP2S30 EP2S60 EP2S90 gx 743 Text: Section II. Clock Management This section provides information on clock management in Stratix II GX devices. It describes the enhanced and fast phase-locked loops PLLs that support clock management and synthesis for on-chip clock management, external system clock management, and high-speed I/O interfaces.	Original		PDF
SH3001IMLTRT Abstract: pseudo-random noise generator Text: SH3001 MicroBuddy Real-Time Clock and Clock Management Support IC for Microcontrollers SYSTEM MANAGEMENT Description Features The programmable SH3001 MicroBuddy™ µBuddy™ provides mandatory microcontroller support functions: ♦ ♦ Clock Management System	Original	SH3001 SH3001, SH3001IMLTRT pseudo-random noise generator	PDF
Untitled Abstract: No abstract text available Text: SH3001 MicroBuddy Real-Time Clock and Clock Management Support IC for Microcontrollers SYSTEM MANAGEMENT PRELIMINARY Description Features The programmable SH3001 MicroBuddy™ µBuddy™ provides mandatory microcontroller support functions: ¨ ¨ Clock Management System	Original	SH3001 SH3001,	PDF
405C Abstract: LVEP224 NB100LVEP224 LQFP-64 thermal pad Text: NB100LVEP224 2.5V/3.3V 1:24 Differential ECL/PECL Clock Driver with Clock Select and Output Enable http://onsemi.com Description The NB100LVEP224 is a low skew 1−to−24 differential clock driver, designed with clock distribution in mind, accepting two clock	Original	NB100LVEP224 NB100LVEP224 1-to-24 NB100LVEP224/D 405C LVEP224 LQFP-64 thermal pad	PDF
EP1C12 Abstract: No abstract text available Text: 6. Using PLLs in Cyclone Devices C51006-1.4 Introduction Cyclone FPGAs offer phase locked loops PLLs and a global clock network for clock management solutions. Cyclone PLLs offer clock multiplication and division, phase shifting, programmable duty cycle,	Original	C51006-1 EP1C12	PDF
LVEP221 Abstract: NB100LVEP221 NB100LVEP221FA NB100LVEP221FAR2 Text: NB100LVEP221 2.5V/3.3V 1:20 Differential HSTL/ECL/PECL Clock Driver The NB100LVEP221 is a low skew 1-to-20 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The two clock inputs are differential	Original	NB100LVEP221 NB100LVEP221 1-to-20 LVEP221 r14525 NB100LVEP221/D NB100LVEP221FA NB100LVEP221FAR2	PDF
LVEP221 Abstract: MC100EP221 NB100LVEP221 Text: NB100LVEP221 2.5V/3.3V 1:20 Differential HSTL/ECL/PECL Clock Driver Description The NB100LVEP221 is a low skew 1−to−20 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The two clock inputs are differential	Original	NB100LVEP221 NB100LVEP221 1-to-20 LVEP221 NB100LVEP221/D MC100EP221	PDF
14.7456MHz crystal Abstract: lcd projector Text: ASM3P2856A ASM3P2856B November 2006 rev0.1 Custom Clock generator for LCD Projector Features Product Description • Custom Clock Generator for LCD Projector ASM3P2856A/B generate the required four custom clock • Generates EMI optimized clock signals for	Original	ASM3P2856A ASM3P2856B ASM3P2856A/B 7456MHz 27MHz 65MHz, 65MHz 14.7456MHz crystal lcd projector	PDF
S5200-1 Abstract: EP1S60 S52001-3 Text: 1. General-Purpose PLLs in Stratix & Stratix GX Devices S52001-3.2 Introduction Stratix and Stratix GX devices have highly versatile phase-locked loops PLLs that provide robust clock management and synthesis for on-chip clock management, external system clock management, and high-speed	Original	S52001-3 S5200-1 EP1S60	PDF
Rambus clock generator Abstract: No abstract text available Text: Direct Rambus Clock Generator ® RAMBUS Overview • The Direct Rambus® Clock Generator DRCG provides the necessary clock signals to support a Direct Rambus memory subsystem. It includes signals to synchronize the Direct Rambus Channel clock to an external system clock. Contained in a 24-pin SSOP	Original	24-pin DL-0056, DL-0056 Rambus clock generator	PDF
automatic change over switch circuit diagram Abstract: EP2S15 EP2S180 EP2S30 EP2S60 EP2S90 RCK7 Text: 1. PLLs in Stratix II & Stratix II GX Devices SII52001-4.4 Introduction Stratix II and Stratix II GX device phase-locked loops PLLs provide robust clock management and synthesis for device clock management, external system clock management, and high-speed I/O interfaces.	Original	SII52001-4 automatic change over switch circuit diagram EP2S15 EP2S180 EP2S30 EP2S60 EP2S90 RCK7	PDF

transistor AJ q16 Abstract: LQFP-64 NB100EP223 NB100EP223FA NB100EP223FAR2 27Q16 LQFP64 test socket Text: NB100EP223 3.3V 1:22 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Output Enable The NB100EP223 is a low skew 1-to-22 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The part is designed for use in low voltage	Original	NB100EP223 NB100EP223 1-to-22 NB100EP223/D transistor AJ q16 LQFP-64 NB100EP223FA NB100EP223FAR2 27Q16 LQFP64 test socket	PDF
RC7100 Abstract: CRYSTAL oscillator 14.318MHZ Text: www.fairchildsemi.com RC7100 100MHz Motherboard System Clock Description • • • • • • The RC7100 is a clock synthesizer for 100MHz operation on Pentium II based motherboard systems. It contains 4 copies of the CPU clock, 8 copies of the PCI clock, 3 copies of the REF clock, 2 copies of the 48MHz	Original	RC7100 100MHz RC7100 48MHz 48MHz 318MHz DS50007100 CRYSTAL oscillator 14.318MHZ	PDF
EP2C20 Abstract: EP2C35 EP2C50 CII51007-3 CLK12 differential ring oscillator SSTL25 Text: Section II. Clock Management This section provides information on the phase-locked loops PLLs . Cyclone II PLLs offer general-purpose clock management with multiplication and phase shifting and also have the ability to drive off chip to control system-level clock networks. This section contains	Original	from10-F EP2C20 EP2C35 EP2C50 CII51007-3 CLK12 differential ring oscillator SSTL25	PDF
SLG505YC264CT Abstract: SLG505YC264 SLG505YC264C Oscilloscope USB 200Mhz Schematic slg silego SLG505YC264CITTR slg505 SLG505YC264CIT 2N3904 BSS138 Text: SLG505YC264C Clock Synthesizer for Intel PCI-Express Gen2 Chipset Features Output Summary • SLG505YC264C is fully compliant to Intel CK505 clock specification revision 1.0 • 2- differential CPU clock outputs @ 0.8V • 1 - selectable differential CPU/SRC clock output @ 0.8V	Original	SLG505YC264C SLG505YC264C CK505 DOT96/SRC 25MHz 576MHz SLG505YC264CT SLG505YC264 Oscilloscope USB 200Mhz Schematic slg silego SLG505YC264CITTR slg505 SLG505YC264CIT 2N3904 BSS138	PDF
Untitled Abstract: No abstract text available Text: Preliminary Information Direct Rambus® Clock Generator RAMBUS Overview The Direct Rambus® Clock Generator DRCG provides the necessary clock signals to support a Direct Rambus memory subsystem. It includes signals to synchronize the Direct Rambus Channel clock to an	Original	24-pin DL-0056, DL-0056	PDF
Slg505yc264bt Abstract: SLG505YC264B Oscilloscope USB 200Mhz Schematic intel ck505 clock specification SLG505YC264 SLG505YC264BTTR TME 57 2N3904 BSS138 CK410 Text: SLG505YC264B Clock Synthesizer for Intel PCI-Express Gen2 Chipset Features Output Summary • SLG505YC264B is fully compliant to Intel CK505 clock specification revision 1.0 • 2- differential CPU clock outputs @ 0.8V • 1 - selectable differential CPU/SRC clock output @ 0.8V	Original	SLG505YC264B SLG505YC264B CK505 DOT96/SRC 25MHz 576MHz 150mV Slg505yc264bt Oscilloscope USB 200Mhz Schematic intel ck505 clock specification SLG505YC264 SLG505YC264BTTR TME 57 2N3904 BSS138 CK410	PDF
SLG505YC256CT Abstract: SLG505YC256 SLG505YC256CIT Oscilloscope USB 200Mhz Schematic SLG505YC256CTTR SLG505YC256C slg silego XTAL 25MHz 20PF 30PPM intel ck505 clock specification 2N3904 Text: SLG505YC256C Clock Synthesizer for Intel PCI-Express Gen2 Chipset Features Output Summary • SLG505YC256C is fully compliant to Intel CK505 clock specification revision 1.0 • 2- differential CPU clock outputs @ 0.8V • 1 - selectable differential CPU/SRC clock output @ 0.8V	Original	SLG505YC256C SLG505YC256C CK505 DOT96/SRC 25MHz 576MHz SLG505YC256CT SLG505YC256 SLG505YC256CIT Oscilloscope USB 200Mhz Schematic SLG505YC256CTTR slg silego XTAL 25MHz 20PF 30PPM intel ck505 clock specification 2N3904	PDF
Untitled Abstract: No abstract text available Text: PCS3P7101A September 2006 rev 0.1 Low Power Peak EMI Reducing clock synthesizer Product Description Features The PCS3P7101A is a low cost, single-output, clock • Generates a 4x low EMI clock at the output synthesizer. The PCS3P7101A generates a 4x output clock	Original	PCS3P7101A PCS3P7101A	PDF
C9714 Abstract: 275 L20 Text: C9714 100 MHz Clock Generator with SSCG and Power Management for Mobile Application Preliminary PRODUCT FEATURES FREQUENCY TABLE T T T T T T Supplies: 2 Ref clocks 2 Host CPU clocks 1 free running and 5 PCI Clocks 1 48MHz fixed clock 1 48 or 24 MHz fixed clock	Original	C9714 48MHz 28-pin SEL48# 48-24M 48-24M/TS# IMIC9714AYB IMIC9714ATB C9714A C9714 275 L20	PDF
Intel 80C286 Abstract: 910U ice28 8086 interrupt vector table 231923 ICE286 Text: in te i 80C286 CHMOS MICROPROCESSOR WITH MEMORY MANAGEMENT AND PROTECTION High Speed CHMOS III Technology 12.5 MHz Clock Rate Pin for Pin, Clock for Clock, and Functionally Compatible with the HMOS 80286 Available in a Variety of Packages: — 68 Pin PLCC Plastic Leaded Chip	OCR Scan	80C286 82C284 82C288 Intel 80C286 910U ice28 8086 interrupt vector table 231923 ICE286	PDF

CLOCK MANAGEMENT Search Results

CLOCK MANAGEMENT Result Highlights (5)

CLOCK MANAGEMENT Datasheets Context Search

49fct3805a

linear handbook

EP1S60

automatic change over switch circuit diagram

SH3001IMLTRT

Untitled

405C

EP1C12

LVEP221

LVEP221

14.7456MHz crystal

S5200-1

Rambus clock generator

automatic change over switch circuit diagram

transistor AJ q16

RC7100

EP2C20

SLG505YC264CT

Untitled

Slg505yc264bt

SLG505YC256CT

Untitled

C9714

Intel 80C286