80C51
Abstract: DIV32 MUL16 XA User Guide DIVU16
Text: 4 CPU Organization This chapter describes the Central Processing Unit CPU of the XA Core. The CPU contains all status and control logic for the XA architecture. The XA reset sequence and the system oscillator interface with the CPU, and power control is handled here. The CPU performs
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16-bit
16-bits
80C51
DIV32
MUL16
XA User Guide
DIVU16
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AT324
Abstract: DIVU32 80C51 DIV32 MUL16 XA User Guide AA55h
Text: 4 CPU Organization This chapter describes the Central Processing Unit CPU of the XA Core. The CPU contains all status and control logic for the XA architecture. The XA reset sequence and the system oscillator interface with the CPU, and power control is handled here. The CPU performs interrupt and
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16-bit
16-bits
AT324
DIVU32
80C51
DIV32
MUL16
XA User Guide
AA55h
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Z08602/Z08614
Abstract: Z08614 Z08602 timers Z86C15 Z86E23 Z86K15 keyboard 40pin
Text: Keyboards/Input Devices Consumer 2/4K ROM Block Diagram Z8 CPU Zilog Superintegration Pr oducts Guide 4K ROM Z8 CPU RAM 8K OTP/ROM RAM Z8 CPU 4K ROM Z8 CPU RAM Counter/Timers Device P1 P2 RAM Z8 CPU RAM Counter/Timers Counter/Timers WDT WDT Counter/Timers
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Z86E23
Z08602/Z08614
Z08615/Z08616
Z86C15
Z86K15/K17
Z08602
Z08614
44-Pin
40-Pin
Z08602/Z08614
timers
Z86C15
Z86E23
Z86K15
keyboard 40pin
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mouse microcontroller
Abstract: z8 cpu OPTO-transistor 6-bit prescaler Z86317 Z86318 Z86C07 optotransistor Z86C84 Z86E04
Text: Consumer Keyboards/Input Devices 1K ROM Z8 CPU Block Diagram 1K ROM RAM Z8 CPU RAM Counter/Timers WDT WDT Comparators P1 Z8 CPU P1 RAM Counter/Timers 2 K ROM Z86317 3 K ROM (Z86318) Z8 CPU RAM CPU Counter/Timers WDT POR A/D D/A WDT Comparators P0 P3 Z86C04/E04
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Z86317)
Z86C04/E04
Z86318)
Z86317/Z86318
Z86C17
Z86C07/C08/E08
Z86C84
Z86E08
Z86E04
86317-PS2
mouse microcontroller
z8 cpu
OPTO-transistor
6-bit prescaler
Z86317
Z86318
Z86C07
optotransistor
Z86C84
Z86E04
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Z180
Abstract: Z380 srca 10bbb Z80 instruction set
Text: Z380 USER'S MANUAL ZILOG USER’s MANUAL CHAPTER 5 INSTRUCTION SET 5.1 INTRODUCTION The Z380™ CPU instruction set is a superset of the Z80 CPU and the Z180 MPU; the Z380 CPU is opcode compatible with the Z80 CPU/Z180 MPU. Thus, a Z80/Z180 program can be executed on a Z380 CPU without modification. The
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Z380TM
Z380TM
CPU/Z180
Z80/Z180
16/32-Bit
DC-8297-03
Z180
Z380
srca 10bbb
Z80 instruction set
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CPU08
Abstract: MC68HC908 AN012302-0608 F64XX MC68HC908AB32 UM0128 LT 505-S adc 8-bit with bcd output CPU08RMAD
Text: Application Note Zilog’s eZ8TM CPU Versus Motorola’s CPU08 - A Comparison Study AN012302-0608 Abstract CPU08 CPU Description Zilog’s eZ8 TM CPU is a high-performance 8-bit microcontroller Central Processor Unit CPU designed to address continuing demand for faster
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CPU08
AN012302-0608
MC68HC908
16-bit
AN012302-0608
F64XX
MC68HC908AB32
UM0128
LT 505-S
adc 8-bit with bcd output
CPU08RMAD
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tqfp 7x7
Abstract: dc shunt motor driver dc motor schematic MCP2515 integrated controller J2602 MCP2515 MLX81100 QFN40 TJA1041 TQFP48
Text: MLX81100 DC-Motor Controller Features CPU o o MelexCM CPU Dual RISC CPU – 5MIPS o LIN protocol controller o 16-bit application CPU Internal RC-Oscillator Memories o o 2kbyte RAM, 30kbyte Flash, 128 byte EEPROM Flash for series production Periphery o o
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MLX81100
16-bit
30kbyte
100-kBaud
100Hz
100kHz
16-channel
10-bit
ISO/TS16949
tqfp 7x7
dc shunt motor
driver dc motor schematic
MCP2515 integrated controller
J2602
MCP2515
MLX81100
QFN40
TJA1041
TQFP48
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R5F61657
Abstract: TFP-120 TQFP-120 CPU H8
Text: Section 1 Overview 1.1 Features • 32-bit high-speed H8SX CPU Upward compatible with the H8/300 CPU, H8/300H CPU, and H8S CPU Object programs for those CPUs are executable Sixteen 16-bit general registers 87 basic instructions • Extensive peripheral functions
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32-bit
H8/300
H8/300H
16-bit
10-bit
R5F61657
R5F61657
TFP-120
TQFP-120
CPU H8
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00FF
Abstract: 1D26
Text: H8/300 Programming Manual Contents Section 1. CPU. 1 1.1 General CPU Architecture. 2
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H8/300
00FF
1D26
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R5S61650
Abstract: TFP-120 TQFP-120
Text: Section 1 Overview 1.1 Features • 32-bit high-speed H8SX CPU Upward compatible with the H8/300 CPU, H8/300H CPU, and H8S CPU Object programs for those CPUs are executable Sixteen 16-bit general registers 87 basic instructions • Extensive peripheral functions
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32-bit
H8/300
H8/300H
16-bit
10-bit
H8SX/1650
R5S61650
R5S61650
TFP-120
TQFP-120
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bpl modem
Abstract: freescale tpms pin diagram of hcs12 microcontroller seven segment 14pin ADC16 HCS08 MC9S08MM128 S08USBV1 MC9S08MM128RM mcg motor 2233
Text: MC9S08MM128 MC9S08MM64 MC9S08MM32 MC9S08MM32A Reference Manual HCS08 Microcontrollers MC9S08MM128RM Rev. 3 07/2010 freescale.com MC9S08MM128 series 8-Bit HCS08 Central Processor Unit CPU Peripherals • Up to 48-MHz CPU above 2.4 V, 40 MHz CPU above 2.1 V, and 20 MHz CPU above
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MC9S08MM128
MC9S08MM64
MC9S08MM32
MC9S08MM32A
HCS08
MC9S08MM128RM
MC9S08MM128
HCS08
48-MHz
bpl modem
freescale tpms
pin diagram of hcs12 microcontroller
seven segment 14pin
ADC16
S08USBV1
MC9S08MM128RM
mcg motor 2233
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MLF 6x6
Abstract: SMD Hall sensors E1 Regulated Power Supply abstract E hall sensor smd 4 pin abstract for communication system cmos sensor abstract E2 p SMD Transistor spi slave JESD22-A113 MLX81100
Text: MLX81100 LIN Slave for FET Control Features CPU o o MelexCM CPU o Dual RISC CPU MLX4/16 – 5MIPS o 4-bit LIN protocol controller o 16-bit application CPU Internal RC-Oscillator Memories o o 2kbyte RAM, 32kbyte Flash, 128 byte EEPROM Flash for series production
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MLX81100
MLX4/16
16-bit
32kbyte
100-kBaud
100Hz
100kHz
16-channel
10-bit
MLF 6x6
SMD Hall sensors E1
Regulated Power Supply abstract
E hall sensor smd 4 pin
abstract for communication system
cmos sensor abstract
E2 p SMD Transistor
spi slave
JESD22-A113
MLX81100
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Untitled
Abstract: No abstract text available
Text: MLX81100 LIN Slave for FET Control Features CPU o o MelexCM CPU o Dual RISC CPU MLX4/16 – 5MIPS o 4-bit LIN protocol controller o 16-bit application CPU Internal RC-Oscillator Memories o o 2kbyte RAM, 32kbyte Flash, 128 byte EEPROM Flash for series production
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MLX81100
MLX4/16
16-bit
32kbyte
100-kBaud
100Hz
100kHz
16-channel
10-bit
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Mlx16
Abstract: Regulated Power Supply abstract MLX4/16 pdf/MLX16
Text: MLX81100 LIN Slave for FET Control Features CPU o o MelexCM CPU o Dual RISC CPU MLX4/16 – 5MIPS o 4-bit LIN protocol controller o 16-bit application CPU Internal RC-Oscillator Memories o o 2kbyte RAM, 32kbyte Flash, 128 byte EEPROM Flash for series production
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MLX81100
MLX4/16
16-bit
32kbyte
100-kBaud
100Hz
100kHz
16-channel
10-bit
Mlx16
Regulated Power Supply abstract
MLX4/16
pdf/MLX16
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16 pin FRC connector
Abstract: Regulated Power Supply abstract iso 7637 transistor p16 MLX81001 FRC 16 PIN connector p15 transistor iso 7637 pulse 5 DTA143 J2602
Text: MLX81001 General Purpose Automotive MCU Features CPU o o MelexCM CPU o Dual RISC CPU MLX4/16 – 5MIPS o 4-bit LIN protocol controller o 16-bit application CPU Internal RC-Oscillator Memories o 2kbyte RAM, 32kbyte Flash, 128 byte EEPROM Periphery o o o o o
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MLX81001
MLX4/16
16-bit
32kbyte
100-kBaud
100Hz
100kHz
10-bit
16 pin FRC connector
Regulated Power Supply abstract
iso 7637
transistor p16
MLX81001
FRC 16 PIN connector
p15 transistor
iso 7637 pulse 5
DTA143
J2602
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diode T35 12H
Abstract: 100NS PQFP144 ST10F167 ST10F167 Controller disassembler st10 Bootstrap
Text: ST10F167 16-BIT MCU WITH 128KBYTE FLASH MEMORY • HIGH PERFORMANCE CPU – 16-BIT CPU WITH 4-STAGE PIPELINE. – 16-BIT CPU WITH 4 STAGE PIPELINE – 100NS INSTRUCTION CYCLE TIME AT 20MHz CPU CLOCK – 500NS MULTIPLICATION 16*16 BIT – 1µS DIVISION (32/16 BIT)
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ST10F167
16-BIT
128KBYTE
100NS
20MHz
500NS
diode T35 12H
PQFP144
ST10F167
ST10F167 Controller
disassembler
st10 Bootstrap
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STP2202ABGA
Abstract: RT0201 Sun Enterprise 250 Sun UltraSparc ULTRASPARC MC100LVE210 SME5224AUPA-400
Text: SME5224AUPA-400 July 1999 UltraSPARC -II CPU Module 400 MHz CPU, 4.0 MB E-Cache DATASHEET MODULE DESCRIPTION The UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module, SME5224AUPA-400 delivers high performance computing in a compact design. Based on the UltraSPARC™-II CPU, this module is designed using a small
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SME5224AUPA-400
SME5224AUPA-400)
STP2202ABGA
RT0201
Sun Enterprise 250
Sun UltraSparc
ULTRASPARC
MC100LVE210
SME5224AUPA-400
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Untitled
Abstract: No abstract text available
Text: SME5224AUPA-400 July 1999 UltraSPARC -II CPU Module 400 MHz CPU, 4.0 MB E-Cache DATASHEET MODULE DESCRIPTION The UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module, SME5224AUPA-400 delivers high performance computing in a compact design. Based on the UltraSPARC™-II CPU, this module is designed using a small
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SME5224AUPA-400
SME5224AUPA-400)
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SPRU190
Abstract: XDS510 SPRU185
Text: TMS320C62xx CPU and Instruction Set Reference Guide 1997 Digital Signal Processing Solutions Printed in U.S.A., January, 1997 D425008–9761 Revision * SPRU189A Reference Guide TMS320C62xx CPU and Instruction Set 1997 TMS320C62xx CPU and Instruction Set Reference Guide
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TMS320C62xx
D425008
SPRU189A
D425008-9761
SPRU190
XDS510
SPRU185
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u cores
Abstract: No abstract text available
Text: Single-chip System CPU Cores Gate Arrays with Built-in CPU Core 8-bit CPU Core (Z80)_ 16-bit CPU Core (V20HL/V30HL) 8-bit CPU Core (Z80/Z80 low power consumption version) Single-chip Systems (CPU Cores) Cell-based ICs (CPU Cores) 16-bit CPU Core (V20HL/V30HL)
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16-bit
V20HL/V30HL)
Z80/Z80
32-bit
V20HL/V30HL
u cores
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TLCS-90
Abstract: TLCS-900 tlcs90 96CM40
Text: T O S H IB A TLCS-900 CPU 900f 900/Lf 900/H CPU Core Different Points There are 3 type CPU core : 0 900, D 900/L, (D 900/H in TLCS-900 series and they are different from following points. CPU Different CPU Operating mode CPU Register mode Interrupt vector formula
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TLCS-900
900/L,
900/H
900/L
t89BH
CPU900-27
TLCS-90
tlcs90
96CM40
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82c51
Abstract: AV to VGA converter
Text: SINGLE-CHIP SYSTEM CPU CORE • CELL-BASED ICs (CPU Cores) New product ★ Under development 5F ASIC • Diversified CPU cores (the SHI 1 and ARM7TDMI) are available. • Select the most suitable CPU in the lineup according to the applications. Macrocell Library
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16-bit
256-byte]
IEEE1284
82C37)
82c51
AV to VGA converter
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TMP-88
Abstract: BUT32
Text: TO SHIBA TM P88C K48/M48 OPERATION 1. CPU Core Functions The CPU core consists of the CPU, system clock control circuit, and interrupt control circuit. This chapter describes the CPU core, program memory, data memory and the reset circuit. 1.1 Memory Address Map
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K48/M48
TMP88CK48/M48
0003F
000BF
000C0
VAREF/256)
TMP-88
BUT32
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Untitled
Abstract: No abstract text available
Text: n = T S G S -IH O M S O N *7 M , [MiMi[Liginia R!ine§ s n om 65BQ1 16-BIT ROMLESS MICROCONTROLLER DATASHEET High performance CPU • 16-bit CPU with 4-stage pipeline ■ 80ns instruction cycle time at 25MHz CPU clock ■ 400ns 16x16 bit multiplication CPU-Core
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65BQ1
16-BIT
25MHz
400ns
16x16
800ns
PQFP100
ST10R165BQ
PQFP100
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