CY2XP304BVIT Search Results

CY2XP304BVIT Datasheets (1)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
CY2XP304BVIT		Cypress Semiconductor	Logic and Timing: High-Frequency Programmable PECL Clock Generation Module: T		Original	PDF

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Catalog Datasheet	MFG & Type	PDF	Document Tags
CY2XP304 Abstract: CY2XP304BVC CY2XP304BVCT CY2XP304BVI CY2XP304BVIT Text: ADVANCE INFORMATION CY2XP304 High-Frequency Programmable PECL Clock Generation Module Features • HSTL inputs—HSTL-to-LVPECL level translation • 125- to 400-MHz output range for high-speed applications 500-MHz option available • Jitter peak-peak (TYPICAL) = 65 ps	Original	PDF	CY2XP304 400-MHz 500-MHz 36-VFBGA, CY2XP304 CY2XP304BVC CY2XP304BVCT CY2XP304BVI CY2XP304BVIT
Untitled Abstract: No abstract text available Text: CY2XP304 High-Frequency Programmable PECL Clock Generation Module Features • HSTL inputs—HSTL-to-LVPECL level translation • 125- to 500-MHz output range for high-speed applications • Period jitter peak-peak = 55 ps max at 125MHz • Four low-skew LVPECL outputs	Original	PDF	CY2XP304 125MHz 500-MHz 36-VFBGA, CY2XP304
413407 Abstract: No abstract text available Text: CY2XP304 High-Frequency Programmable PECL Clock Generation Module Features • HSTL inputs—HSTL-to-LVPECL level translation • 40 ps typical peak-peak period jitter at 125 MHz • 125- to 500-MHz output range for high-speed applications • 30 ps typical output-output skew at 400 MHz	Original	PDF	CY2XP304 500-MHz 36-VFBGA, CY2XP304 413407
CY2XP304 Abstract: CY2XP304BVC CY2XP304BVCT CY2XP304BVI CY2XP304BVIT Text: CY2XP304 High-Frequency Programmable PECL Clock Generation Module Features • HSTL inputs—HSTL-to-LVPECL level translation • 125- to 500-MHz output range for high-speed applications • Period jitter peak-peak 125MHz max. = 55 ps • Four low-skew LVPECL outputs	Original	PDF	CY2XP304 500-MHz 125MHz 36-VFBGA, CY2XP304 CY2XP304BVC CY2XP304BVCT CY2XP304BVI CY2XP304BVIT