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    CY7C1373 Price and Stock

    Infineon Technologies AG CY7C1373KV33-133AXI

    IC SRAM 18MBIT PARALLEL 100TQFP
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    DigiKey CY7C1373KV33-133AXI Tray 71 1
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    Mouser Electronics CY7C1373KV33-133AXI 71
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    Rochester Electronics CY7C1373KV33-133AXI 2,575 1
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    Rochester Electronics LLC CY7C1373B-83BZC

    IC SRAM 18MBIT PAR 83MHZ 165FBGA
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    DigiKey CY7C1373B-83BZC Bulk 9
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    Infineon Technologies AG CY7C1373D-133BZI

    IC SRAM 18MBIT PARALLEL 165FBGA
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    Rochester Electronics LLC CY7C1373D-133BZI

    IC SRAM 18MBIT PARALLEL 165FBGA
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    DigiKey CY7C1373D-133BZI Tray 11
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    Infineon Technologies AG CY7C1373D-100AXC

    IC SRAM 18MBIT PAR 100TQFP
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    DigiKey CY7C1373D-100AXC Tray 72
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    CY7C1373 Datasheets (51)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CY7C1373B Cypress Semiconductor 512K x 36/1M x 18 Flow-Thru SRAM with NoBL Architecture Original PDF
    CY7C1373B-117AC Cypress Semiconductor 512K x 36/1M x 18 Flow-Thru SRAM with NoBL Architecture Original PDF
    CY7C1373BV25 Cypress Semiconductor 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Original PDF
    CY7C1373C Cypress Semiconductor 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture Original PDF
    CY7C1373C-100AC Cypress Semiconductor 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture Original PDF
    CY7C1373C-100AI Cypress Semiconductor Original PDF
    CY7C1373C-100BGC Cypress Semiconductor 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture Original PDF
    CY7C1373C-100BZC Cypress Semiconductor 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture Original PDF
    CY7C1373C-100BZI Cypress Semiconductor Original PDF
    CY7C1373C-117AC Cypress Semiconductor Original PDF
    CY7C1373C-117AI Cypress Semiconductor Original PDF
    CY7C1373C-117BGC Cypress Semiconductor Original PDF
    CY7C1373C-117BGI Cypress Semiconductor Original PDF
    CY7C1373C-117BZC Cypress Semiconductor Original PDF
    CY7C1373C-117BZI Cypress Semiconductor Original PDF
    CY7C1373C-133AC Cypress Semiconductor 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture Original PDF
    CY7C1373C-133AI Cypress Semiconductor Original PDF
    CY7C1373C-133BGC Cypress Semiconductor Original PDF
    CY7C1373C-133BGI Cypress Semiconductor Original PDF
    CY7C1373C-133BZC Cypress Semiconductor Original PDF

    CY7C1373 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1371C CY7C1373C 18-Mb 512K x 36/1M x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero


    Original     		CY7C1371C CY7C1373C 18-Mb 36/1M 133-MHz 117-MHz 100-MHz PDF

    CY7C1371

    Abstract: CY7C1371B CY7C1373 CY7C1373B
    Text: CY7C1371B CY7C1373B 73B 512K x 36/1M x 18 Flow-Thru SRAM with NoBL Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT devices • Supports 117-MHz bus operations with zero wait states — Data is transferred on every clock


    Original     		CY7C1371B CY7C1373B 36/1M 117-MHz 100-MHz 83-MHz CY7C1371B/CY7C1373B CY7C1371 CY7C1371B CY7C1373 CY7C1373B PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1373B CY7C1371B CY7C1373B PRELIMINARY 512Kx36/1Mx18 Flow-Thru SRAM with NoBL Architecture Features spectively, designed to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371B/CY7C1373B are equipped with the advanced No


    Original     		1CY7C1373B CY7C1371B CY7C1373B 512Kx36/1Mx18 CY7C1371B/CY7C1373B PDF

    CY7C1371D

    Abstract: CY7C1373D
    Text: PRELIMINARY CY7C1371D CY7C1373D 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero


    Original     		CY7C1371D CY7C1373D 18-Mbit 36/1M 133-MHz 100-MHz CY7C1371D/CY7C1373D CY7C1371D CY7C1373D PDF

    aag3

    Abstract: CY7C1371 j7m1
    Text: CY7C1371A CY7C1373A PRELIMINARY 512Kx36/1Mx18 Flow-Thru SRAM with NoBL Architecture Features signed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371A/CY7C1373A is equipped with the advanced No


    Original     		CY7C1371A CY7C1373A 512Kx36/1Mx18 CY7C1371A/CY7C1373A CY7C1371A/ CY7C1373A 117-MHz aag3 CY7C1371 j7m1 PDF

    cy7c1371b-100ai

    Abstract: CY7C1371 CY7C1371B CY7C1373B CY7C1371B-117AC
    Text: CY7C1371B CY7C1373B 73B 512K x 36/1M x 18 Flow-Thru SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT devices • Supports 117-MHz bus operations with zero wait states — Data is transferred on every clock


    Original     		CY7C1371B CY7C1373B 36/1M 117-MHz 100-MHz 83-MHz CY7C1371B/CY7C1373B cy7c1371b-100ai CY7C1371 CY7C1371B CY7C1373B CY7C1371B-117AC PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1371DV25 CY7C1373DV25 PRELIMINARY 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero


    Original     		CY7C1371DV25 CY7C1373DV25 18-Mbit 36/1M 133-MHz 100-MHz PDF

    CY7C1371C

    Abstract: CY7C1371CV25 CY7C1373CV25 CY7C1371
    Text: CY7C1373CV25 CY7C1371CV25 PRELIMINARY 512K x 36/1M x 18 Flow-Thru SRAM with NoBL Architecture Features • Pin compatible and functionally equivalent to ZBT devices • Supports 133-MHz bus operations with zero wait states — Data is transferred on every clock


    Original     		CY7C1373CV25 CY7C1371CV25 36/1M 133-MHz 117-MHz 100-MHz CY7C1371CV25/CY7C1373CV25 CY7C1371C CY7C1371CV25 CY7C1373CV25 CY7C1371 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1371D CY7C1373D 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero


    Original     		CY7C1371D CY7C1373D 18-Mbit 36/1M 133-MHz 100-MHz PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1371DV25 CY7C1373DV25 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero


    Original     		CY7C1371DV25 CY7C1373DV25 18-Mbit 36/1M 133-MHz 100-MHz CY7C1373DV25 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1373BV25 CY7C1371BV25 CY7C1373BV25 PRELIMINARY 512Kx36/1Mx18 Flow-Thru SRAM with NoBL Architecture Features respectively, designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371BV25/CY7C1373BV25 is


    Original     		1CY7C1373BV25 CY7C1371BV25 CY7C1373BV25 512Kx36/1Mx18 133-MHz 117-MHz 100-MHz PDF

    CY7C1371D-100AXI

    Abstract: CY7C1371D CY7C1373D
    Text: CY7C1371D CY7C1373D 18-Mbit 512K x 36/1Mbit x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles • Supports up to 133-MHz bus operations with zero wait


    Original     		CY7C1371D CY7C1373D 18-Mbit 36/1Mbit 133-MHz CY7C1371D-100AXI CY7C1371D CY7C1373D PDF

    CY7C1371DV25

    Abstract: CY7C1373DV25
    Text: CY7C1371DV25 CY7C1373DV25 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Supports up to 133-MHz bus operations with zero wait


    Original     		CY7C1371DV25 CY7C1373DV25 18-Mbit 36/1M 133-MHz CY7C1371DV25/CY7C1373DV25 CY7C1371DV25 CY7C1373DV25 PDF

    662k

    Abstract: CY7C1371DV25 CY7C1371DV25-133AXC CY7C1373DV25
    Text: CY7C1371DV25 CY7C1373DV25 PRELIMINARY 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero


    Original     		CY7C1371DV25 CY7C1373DV25 18-Mbit 36/1M 133-MHz CY7C1371DV25/CY7C1373DV25 662k CY7C1371DV25 CY7C1371DV25-133AXC CY7C1373DV25 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1371B CY7C1373B 73B 512K x 36/1M x 18 Flow-Thru SRAM with NoBL Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT devices • Supports 117-MHz bus operations with zero wait states — Data is transferred on every clock


    Original     		CY7C1371B CY7C1373B 36/1M 117-MHz 100-MHz 83-MHz CY7C1371B/CY7C1373B PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1371D CY7C1373D 18-Mbit 512 K x 36/1 M × 18 Flow-Through SRAM with NoBL Architecture 18-Mbit (512 K × 36/1 M × 18) Flow-through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency (NoBL) architecture eliminates dead cycles


    Original     		CY7C1371D CY7C1373D 18-Mbit 133-MHz PDF

    CY7C1371

    Abstract: CY7C1371BV25 CY7C1373BV25
    Text: CY7C1373BV25 CY7C1371BV25 512K x 36/1M x 18 Flow-Thru SRAM with NoBL Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT devices • Supports 117-MHz bus operations with zero wait states — Data is transferred on every clock


    Original     		CY7C1373BV25 CY7C1371BV25 36/1M 117-MHz CY7C1371BV25 CY7C1373BV25 CY7C1371 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1371D CY7C1373D 18-Mbit 512 K x 36/1 M × 18 Flow-through SRAM with NoBL Architecture 18-Mbit (512 K × 36/1 M × 18) Flow-through SRAM with NoBL™ Architecture Features Functional Description[1] • No Bus Latency (NoBL) architecture eliminates dead


    Original     		CY7C1371D CY7C1373D 18-Mbit CY7C1371D/CY7C1373D PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1371CV25 CY7C1373CV25 18-Mb 512K x 36/1M x 18 Flow-through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles. • Can support up to 133-MHz bus operations with zero


    Original     		CY7C1371CV25 CY7C1373CV25 18-Mb 36/1M 133-MHz 117-MHz 100-MHz PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1371D CY7C1373D 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero


    Original     		CY7C1371D CY7C1373D 18-Mbit 36/1M 133-MHz PDF

    Untitled

    Abstract: No abstract text available
    Text: 373C CY7C1371C CY7C1373C PRELIMINARY 512Kx36/1Mx18 Flow-Through SRAM with NoBL Architecture Features • Pin compatible and functionally equivalent to ZBT devices • Supports 133-MHz bus operations with zero wait states — Data is transferred on every clock


    Original     		CY7C1371C CY7C1373C 512Kx36/1Mx18 133-MHz 117-MHz 100-MHz 100-pin PDF

    CY7C1371

    Abstract: CY7C1371C CY7C1371CV25 CY7C1373CV25
    Text: CY7C1373CV25 CY7C1371CV25 PRELIMINARY 512K x 36/1M x 18 Flow-Thru SRAM with NoBL Architecture Features • Pin compatible and functionally equivalent to ZBT devices • Supports 133-MHz bus operations with zero wait states — Data is transferred on every clock


    Original     		CY7C1373CV25 CY7C1371CV25 36/1M 133-MHz 117-MHz 100-MHz CY7C1371CV25/CY7C1373CV25 CY7C1371 CY7C1371C CY7C1371CV25 CY7C1373CV25 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1371D CY7C1373D 18-Mbit 512 K x 36/1 M × 18 Flow-Through SRAM with NoBL Architecture 18-Mbit (512 K × 36/1 M × 18) Flow-through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency (NoBL) architecture eliminates dead cycles


    Original     		CY7C1371D CY7C1373D 18-Mbit CY7C1371D/CY7C1373D PDF

    CY7C1373B-100BZC

    Abstract: No abstract text available
    Text: CY7C1373BV25 CY7C1371BV25 512K x 36/1M x 18 Flow-Thru SRAM with NoBL Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT devices • Supports 117-MHz bus operations with zero wait states — Data is transferred on every clock


    Original     		CY7C1373BV25 CY7C1371BV25 36/1M 117-MHz CY7C1371BV25 CY7C1373BV25 Read/71BV25 CY7C1371BV25/CY7C1373BV25 CY7C1373B-100BZC PDF