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    Untitled

    Abstract: No abstract text available
    Text:  CY7C1392KV18, CY7C1992KV18 CY7C1393KV18, CY7C1394KV18 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features Functional Description • 18 Mbit density 2 M x 8, 2 M x 9, 1 M x 18, 512 K x 36 ■ 333-MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency


    Original     		PDF CY7C1392KV18, CY7C1992KV18 CY7C1393KV18, CY7C1394KV18 18-Mbit 333-MHz

    Untitled

    Abstract: No abstract text available
    Text: CY7C1392KV18, CY7C1992KV18 CY7C1393KV18, CY7C1394KV18 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features Functional Description • 18 Mbit density 2 M x 8, 2 M x 9, 1 M x 18, 512 K x 36 ■ 333-MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency


    Original     		PDF CY7C1392KV18, CY7C1992KV18 CY7C1393KV18, CY7C1394KV18 18-Mbit CY7C1992KV18, CY7C1394KV18

    Untitled

    Abstract: No abstract text available
    Text: CY7C1392KV18 CY7C1393KV18 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features Configurations • 18-Mbit density 2 M x 8, 1 M × 18 CY7C1392KV18 – 2 M × 8 ■ 333-MHz clock for high bandwidth


    Original     		PDF CY7C1392KV18 CY7C1393KV18 18-Mbit 333-MHz

    Untitled

    Abstract: No abstract text available
    Text: CY7C1392KV18 CY7C1393KV18 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features Configurations • 18-Mbit density 2 M x 8, 1 M × 18 CY7C1392KV18 – 2 M × 8 ■ 333-MHz clock for high bandwidth


    Original     		PDF CY7C1392KV18 CY7C1393KV18 18-Mbit CY7C1392KV18 333-MHz

    Untitled

    Abstract: No abstract text available
    Text: CY7C1392KV18 CY7C1393KV18 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features Configurations • 18-Mbit density 2 M x 8, 1 M × 18 CY7C1392KV18 – 2 M × 8 ■ 333-MHz clock for high bandwidth


    Original     		PDF CY7C1392KV18 CY7C1393KV18 18-Mbit CY7C1392KV18 333-MHz

    Untitled

    Abstract: No abstract text available
    Text: CY7C1392KV18 CY7C1393KV18 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features Configurations • 18-Mbit density 2 M x 8, 1 M × 18 CY7C1392KV18 – 2 M × 8 ■ 333-MHz clock for high bandwidth


    Original     		PDF CY7C1392KV18 CY7C1393KV18 18-Mbit 333-MHz