Untitled
Abstract: No abstract text available
Text: CY7C1422JV18, CY7C1429JV18 CY7C1423JV18, CY7C1424JV18 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features Functional Description • 36 Mbit density 4M x 8, 4M x 9, 2M x 18, 1M x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency
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Original
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PDF
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CY7C1422JV18,
CY7C1429JV18
CY7C1423JV18,
CY7C1424JV18
36-Mbit
CY7C1429JV18,
CY7C1424JV18
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z0 150 79
Abstract: No abstract text available
Text: THIS SPEC IS OBSOLETE Spec No: 001-44699 Spec Title: CY7C1422JV18/CY7C1429JV18/CY7C1423JV18/ CY7C1424JV18, 36-MBIT DDR-II SIO SRAM 2-WORD BURST ARCHITECTURE Sunset Owner: Jayasree Nayar NJY Replaced by: None CY7C1422JV18, CY7C1429JV18 CY7C1423JV18, CY7C1424JV18
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Original
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PDF
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CY7C1422JV18/CY7C1429JV18/CY7C1423JV18/
CY7C1424JV18,
36-MBIT
CY7C1422JV18,
CY7C1429JV18
CY7C1423JV18,
CY7C1424JV18
CY7C1429JV18,
z0 150 79
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tms 980
Abstract: No abstract text available
Text: CY7C1422JV18, CY7C1429JV18 CY7C1423JV18, CY7C1424JV18 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features Functional Description • 36 Mbit density 4M x 8, 4M x 9, 2M x 18, 1M x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency
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Original
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PDF
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CY7C1422JV18,
CY7C1429JV18
CY7C1423JV18,
CY7C1424JV18
36-Mbit
tms 980
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Echo
Abstract: No abstract text available
Text: CY7C1422JV18, CY7C1429JV18 CY7C1423JV18, CY7C1424JV18 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features Functional Description • 36 Mbit density 4M x 8, 4M x 9, 2M x 18, 1M x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency
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Original
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PDF
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CY7C1422JV18,
CY7C1429JV18
CY7C1423JV18,
CY7C1424JV18
36-Mbit
Echo
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