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    CYPRESS NOBL 1-MBIT SRAM Search Results

    CYPRESS NOBL 1-MBIT SRAM Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    AT49BV640D-70CI Rochester Electronics LLC AT49BV640D - 64-Mbit (4M x 16), Sectored Flash Visit Rochester Electronics LLC Buy
    MD2114A-5 Rochester Electronics LLC SRAM Visit Rochester Electronics LLC Buy
    HM3-6504B-9 Rochester Electronics LLC Standard SRAM, 4KX1, 220ns, CMOS, PDIP18 Visit Rochester Electronics LLC Buy
    HM1-6516-9 Rochester Electronics LLC Standard SRAM, 2KX8, 200ns, CMOS, CDIP24 Visit Rochester Electronics LLC Buy
    27S03ADM/B Rochester Electronics LLC 27S03A - SRAM Visit Rochester Electronics LLC Buy

    CYPRESS NOBL 1-MBIT SRAM Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: For Immediate Release Cypress Extends Networking SRAM Portfolio To 9 Mbit Density Family Extension Includes Best-in-Class 200 MHz, 3.3V and 2.5V Families; First Parts to Be Manufactured In High-Volume In Cypress’s New 0.2-Micron Process SAN JOSE, Calif., July 19, 2000 – Cypress Semiconductor Corp. NYSE:CY today expanded its family of


    Original     		PDF

    CY7C1329

    Abstract: CY7C1345
    Text: PRESS RELEASE CYPRESS INTRODUCES HIGH-SPEED SYNCHRONOUS SRAM FAMILY Broadens SRAM Market Coverage with New Devices SAN JOSE, Calif., August 17, 1998 - Cypress Semiconductor today introduced a family of high-speed synchronous SRAMs targeted at network and Digital Signal Processor DSP


    Original     		PDF

    Untitled

    Abstract: No abstract text available
    Text: For Immediate Release Cypress Extends Networking SRAM Portfolio to 18 Mbit Density Synchronous and NoBL Memories Target Next-Generation Networking, Telecom Applications SAN JOSE, Calif., August 11, 2000 - Cypress Semiconductor Corp. NYSE:CY today extended its


    Original     		PDF 18-Mbit

    SRAM 6T

    Abstract: No abstract text available
    Text: For Immediate Release Cypress Announces 0.15-micron Technology RAM7 Technology Achieves 8 Mb Yield with the World’s Smallest SRAM Cell SAN JOSE, Calif., August 7, 2000 – Cypress Semiconductor NYSE: CY today announced that its new 0.15-micron RAM7™ process technology has achieved functional silicon of the world’s smallest 8 Mbit


    Original     		PDF 15-micron SRAM 6T

    CY62136V

    Abstract: CY62138V
    Text: PRESS RELEASE CYPRESS'S NEW MoBL SRAMS SET NEW BENCHMARK FOR LOW-POWER 0.25-Micron Devices Offer the Industry’s Lowest Power Consumption SAN JOSE, Calif., December 7, 1998 – Cypress Semiconductor Corp. [NYSE:CY] today introduced a new family of micropower SRAMs with the industry’s lowest power consumption.


    Original     		PDF 25-Micron 000-unit CY62136V CY62138V

    Untitled

    Abstract: No abstract text available
    Text: Press Release CYPRESS'S NEW MoBL SRAMS SET NEW BENCHMARK FOR LOW POWER 0.25-Micron Devices Offer the Industry’s Lowest Power Consumption SAN JOSE, Calif., December 7, 1998 – Cypress Semiconductor Corp. [NYSE:CY] today introduced a new family of micropower SRAMs with the industry’s lowest power consumption. Cypress’s MoBL™ More Battery Life™


    Original     		PDF 25-Micron 000-unit

    4T2R

    Abstract: 4t2r sram cell
    Text: For Immediate Release CYPRESS INTRODUCES 0.2-MICRON PROCESS Rapid Progress Provides Company With Competitive Advantage in Process Technology SAN JOSE, Calif., March 15, 2000 – Cypress Semiconductor today announced that its new 0.2-micron RAM6 technology is now yielding in its high-volume, 8-inch fabrication facility in Bloomington,


    Original     		PDF

    CY7C1371D

    Abstract: CY7C1373D
    Text: PRELIMINARY CY7C1371D CY7C1373D 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero


    Original     		PDF CY7C1371D CY7C1373D 18-Mbit 36/1M 133-MHz 100-MHz CY7C1371D/CY7C1373D CY7C1371D CY7C1373D

    D4C4

    Abstract: No abstract text available
    Text: CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 PRELIMINARY 36-Mbit 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™ The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V,


    Original     		PDF CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 36-Mbit 36/2M 18/512K 250-MHz 200-MHz 167-MHz D4C4

    b1064

    Abstract: CY7C1460AV33 CY7C1460AV33-250 CY7C1462AV33 CY7C1464AV33 u946 K1126 B897 J1127
    Text: CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 PRELIMINARY 36-Mbit 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™ The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V,


    Original     		PDF CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 36-Mbit 36/2M 18/512K CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 CY7C1460AV33/ CY7C1462AV33/CY7C1464AV33 100-Pin b1064 CY7C1460AV33 CY7C1460AV33-250 CY7C1462AV33 CY7C1464AV33 u946 K1126 B897 J1127

    Untitled

    Abstract: No abstract text available
    Text: CY7C1371D CY7C1373D 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero


    Original     		PDF CY7C1371D CY7C1373D 18-Mbit 36/1M 133-MHz 100-MHz

    Untitled

    Abstract: No abstract text available
    Text: CY7C1461AV25 CY7C1463AV25 CY7C1465AV25 PRELIMINARY 36-Mbit 1M x 36/2M x 18/512K x 72 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles


    Original     		PDF CY7C1461AV25 CY7C1463AV25 CY7C1465AV25 36-Mbit 36/2M 18/512K 133-MHz 100-MHz

    05353

    Abstract: CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 b669
    Text: CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 36 Mbit 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT ■ Supports 250 MHz Bus Operations with Zero Wait States


    Original     		PDF CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 36/2M 18/512K CY7C1460AV33nts 05353 CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 b669

    K972

    Abstract: CY7C1460AV25 CY7C1460AV25-250 CY7C1462AV25 CY7C1464AV25 u946 B897 m1124
    Text: CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 PRELIMINARY 36-Mbit 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™ • Supports 250-MHz bus operations with zero wait states


    Original     		PDF CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 36-Mbit 36/2M 18/512K 250-MHz 200-MHz 167-MHz K972 CY7C1460AV25 CY7C1460AV25-250 CY7C1462AV25 CY7C1464AV25 u946 B897 m1124

    CY7C1461AV25

    Abstract: CY7C1463AV25 CY7C1465AV25 1N611 B897
    Text: CY7C1461AV25 CY7C1463AV25 CY7C1465AV25 PRELIMINARY 36-Mbit 1M x 36/2M x 18/512K x 72 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles


    Original     		PDF CY7C1461AV25 CY7C1463AV25 CY7C1465AV25 36-Mbit 36/2M 18/512K 133-MHz 100-MHz CY7C1461AV25 CY7C1463AV25 CY7C1465AV25 1N611 B897

    Untitled

    Abstract: No abstract text available
    Text: CY7C1461AV33 CY7C1463AV33 CY7C1465AV33 PRELIMINARY 36-Mbit 1M x 36/2 M x 18/512K x 72 Flow-Through SRAM with NoBL Architecture Features • JTAG boundary scan for BGA and fBGA packages • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles.


    Original     		PDF CY7C1461AV33 CY7C1463AV33 CY7C1465AV33 36-Mbit 18/512K 133-MHz 100-MHz

    CY7C1355C

    Abstract: CY7C1357C 38T5
    Text: CY7C1355C, CY7C1357C 9-Mbit 256K x 36/512K x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles ■ Can support up to 133-MHz bus operations with zero wait


    Original     		PDF CY7C1355C, CY7C1357C 36/512K 133-MHz CY7C1355C CY7C1357C 38T5

    CY7C1470BV33

    Abstract: CY7C1472BV33 CY7C1474BV33
    Text: CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 72 Mbit 2M x 36/4M x 18/1M x 72 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™ ■ Supports 250 MHz bus operations with zero wait states


    Original     		PDF CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 36/4M 18/1M CY7C1470BV33, CY7C1470BV33 CY7C1472BV33 CY7C1474BV33

    BWSE

    Abstract: bb209a
    Text: CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 PRELIMINARY 36-Mbit 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™ • Supports 250-MHz bus operations with zero wait states


    Original     		PDF CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 36-Mbit 36/2M 18/512K 250-MHz 200-MHz 167-MHz BWSE bb209a

    Untitled

    Abstract: No abstract text available
    Text: CY7C1355C CY7C1357C 9-Mbit 256K x 36/512K x 18 Flow-Through SRAM with NoBL Architecture Features • JTAG boundary scan for BGA and fBGA packages • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero


    Original     		PDF CY7C1355C CY7C1357C 36/512K 133-MHz 100-MHz 100-Pin

    Untitled

    Abstract: No abstract text available
    Text: CY7C1371DV25 CY7C1373DV25 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero


    Original     		PDF CY7C1371DV25 CY7C1373DV25 18-Mbit 36/1M 133-MHz 100-MHz CY7C1373DV25

    662k

    Abstract: CY7C1371DV25 CY7C1371DV25-133AXC CY7C1373DV25
    Text: CY7C1371DV25 CY7C1373DV25 PRELIMINARY 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero


    Original     		PDF CY7C1371DV25 CY7C1373DV25 18-Mbit 36/1M 133-MHz CY7C1371DV25/CY7C1373DV25 662k CY7C1371DV25 CY7C1371DV25-133AXC CY7C1373DV25

    CY7C1355C

    Abstract: No abstract text available
    Text: CY7C1355C CY7C1357C 9-Mbit 256K x 36/512K x 18 Flow-Through SRAM with NoBL Architecture Features • JTAG boundary scan for BGA and fBGA packages • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero


    Original     		PDF CY7C1355C CY7C1357C 36/512K 133-MHz 100-MHz 100-Pin

    Untitled

    Abstract: No abstract text available
    Text: CY7C1355C CY7C1357C 9-Mbit 256K x 36/512K x 18 Flow-Through SRAM with NoBL Architecture Features • JTAG boundary scan for BGA and fBGA packages • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero


    Original     		PDF CY7C1355C CY7C1357C 36/512K 133-MHz 100-MHz 100-Pin