DATA INPUT Search Results

DATA INPUT Result Highlights (5)

Part	Manufacturer	Description
54F157/BFA	Rochester Electronics LLC	DATA SEL/MULTIPLEXER; QUAD 2-INPUT
NFMJMPC226R0G3D	Murata Manufacturing Co Ltd	Data Line Filter,
DCL541A01	Toshiba Electronic Devices & Storage Corporation	Digital Isolator / VDD=2.25~5.5V / 150Mbps / 4 channel(F:R=3:1) / Default Output Logic: Low / Input disable
DCL541B01	Toshiba Electronic Devices & Storage Corporation	Digital Isolator / VDD=2.25~5.5V / 150Mbps / 4 channel(F:R=3:1) / Default Output Logic: High / Input disable
TLX9188	Toshiba Electronic Devices & Storage Corporation	Photocoupler (phototransistor output), DC input, 3750 Vrms, SO6, Automotive

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Phoenix Contact RAD-ISM-900-DATA-BD-PLUS Wireless transceiver (transmitter and receiver) with RS-232, RS-485/RS-422 interface, for 900 MHz ISM band (America). Allows up to 8 analog/digital/pulse inputs and 4 outputs onboard.
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Onlinecomponents.com	RAD-ISM-900-DATA-BD-PLUS					1 $2565.34 10 $2426.08 100 $2426.08 1000 $2426.08 10000 $2426.08	Buy Now

DATA INPUT Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
DM74S151 Abstract: DM74S151N DM54S151J DM54S151W J16A N16E S151 W16A Text: DM74S151 1-of-8 Data Selector/Multiplexer with Complementary Outputs General Description These data selectors/multiplexers contain full on-chip decoding to select the desired data source. The ’S151 selects one-of-eight data sources. The ’S151 has a strobe input	Original	DM74S151 DM74S151 DM74S151N DM54S151J DM54S151W J16A N16E S151 W16A	PDF
LV8153 Abstract: RFID serial Text: SN74LV8153 SERIALĆTOĆPARALLEL INTERFACE www.ti.com SCLS555 − JUNE 2004 DESCRIPTION The SN74LV8153 is a serial-to-parallel data converter. It accepts serial input data and outputs 8-bit parallel data. The automatic data-rate detection feature of the SN74LV8153 eliminates the need for an external oscillator	Original	SN74LV8153 SCLS555 LV8153 RFID serial	PDF
DM74ALS153 Abstract: DM74ALS153N DM74ALS153SJ M16A M16D N16A DM74ALS DM74ALS153M Text: DM74ALS153 Dual 1 of 4 Line Data Selector/Multiplexer General Description Features This Data Selector/Multiplexer contains full on-chip decoding to select one-of-four data sources as a result of a unique two-bit binary code at the Select inputs. Each of the two Data	Original	DM74ALS153 DM74ALS153 DM74ALS153N DM74ALS153SJ M16A M16D N16A DM74ALS DM74ALS153M	PDF
Untitled Abstract: No abstract text available Text: ESMT M13S128168A DDR SDRAM 2M x 16 Bit x 4 Banks Double Data Rate SDRAM Features z JEDEC Standard z Internal pipelined double-data-rate architecture, two data access per clock cycle z Bi-directional data strobe DQS z On-chip DLL z Differential clock inputs (CLK and CLK )	Original	M13S128168A	PDF
j16a Abstract: LS157 54LS157DMQB 54LS157FMQB 54LS157LMQB DM54LS157J DM54LS157W LS158 dm74 quad 4 input dm74ls157 Text: DM74LS157/DM74LS158 Quad 2-Line to 1-Line Data Selectors/Multiplexers General Description n Source programmable counters These data selectors/multiplexers contain inverters and drivers to supply full on-chip data selection to the four output gates. A separate strobe input is provided. A 4-bit word is selected from one of two sources and is routed to the four outputs. The LS157 presents true data whereas the LS158 presents inverted data to minimize propagation delay time.	Original	DM74LS157/DM74LS158 LS157 LS158 j16a 54LS157DMQB 54LS157FMQB 54LS157LMQB DM54LS157J DM54LS157W dm74 quad 4 input dm74ls157	PDF
16 chanel input analog multiplexer Abstract: mzp b 001 49 Relies mzp a 002 44 05 zeranin 020C AS8500 AS8501 G100 MR15 SOIC16 Text: 1.1 2 AS8500 Universal multi pupose data aquisition system Data Sheet 3 DATA SHEET 1 Features INTERNAL TEMPERATURE 16 bits resolution differential inputs Single + 5V supply Low power 15 mW SOIC16 package 16 kHz maximum sampling frequency internal temperature measurement	Original	AS8500 SOIC16 08-Junel-06 16 chanel input analog multiplexer mzp b 001 49 Relies mzp a 002 44 05 zeranin 020C AS8500 AS8501 G100 MR15	PDF
DDR200 Abstract: DDR266 DDR333 256mb ddr333 200 pin K4H560438D Text: 256Mb sTSOPII DDR SDRAM Key Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe DQS • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition	Original	256Mb 8K/64ms 54pin DDR200 DDR266 DDR333 256mb ddr333 200 pin K4H560438D	PDF
K4H5 Abstract: K4H561638D 256mb ddr333 200 pin K4H561638D-TC Text: 256Mb DDR SDRAM Key Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe DQS • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition	Original	256Mb 8K/64ms 66pin K4H5 K4H561638D 256mb ddr333 200 pin K4H561638D-TC	PDF
RDF-960 Abstract: No abstract text available Text: ERA-1 Performance Data NOTE: Use PDF Bookmarks to view DATA at required conditions TYPE: MMIC Amplifier MODEL: ERA-1 Reference Data: RDF-960 S PARAMETERS are presented in dB/deg Format TEST CONDITIONS: INPUT POWER = -15dBm, Icc = 40mA, Vd = 3.43V @Temperature = +25degC	Original	RDF-960 -15dBm, 25degC RDF-960	PDF
LS257 Abstract: LS157 STROBE 1N3064 1N916 LS157 SL74LS157 SL74LS157D SL74LS157N LS257 STROBE Text: SL74LS157 Quad 2-Input Data Selector/Multiplexer This monolitic data selector/multiplexer contains inverters and drivers to supply full on-chip data selection to the four output gates. A separate strobe input is provided. A 4-bit word is selected from one of	Original	SL74LS157 LS157 LS257 SL74LS157N SL74LS157D 1N916 1N3064. LS157 STROBE 1N3064 SL74LS157 LS257 STROBE	PDF
ALS157 Abstract: DM74ALS157M DM74ALS158M M16A M16D N16A DM74ALS157 Text: DM74ALS157/DM74ALS158 Quad 1 of 2 Line Data Selector/Multiplexer General Description These data selectors/multiplexers contain inverters and drivers to supply full on-chip data selection to the four output gates. A separate strobe input is provided. A 4-bit word is selected from one of two sources and is routed to the four outputs. The ALS157 presents true data whereas the ALS158	Original	DM74ALS157/DM74ALS158 ALS157 ALS158 DM74ALS157M DM74ALS158M M16A M16D N16A DM74ALS157	PDF
ADSP21267 Abstract: ADSP-21267 Text: SHARC Processor ADSP-21267 Preliminary Technical Data SUMMARY DAI incorporates two precision clock generators PCG , and an input data port (IDP) that includes a parallel data acquisition port (PDAP), and three programmable timers, all under software control by the signal routing unit (SRU)	Original	ADSP-21267 ADSP-21267 32-bit/40-bit 144-Lead 136-Lead PR04623-0-1/04 ADSP21267	PDF
D2822 Abstract: SN74AS850A ALS138 SN74AS851B Text: SN74AS850A, SN74AS851B 1 OF 16 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS SDAS154A – D2822, DECEMBER 1983 – REVISED JANUARY 1990 • • • • • • • 4-Line to 1-Line Data Selectors/Multiplexers That Can Select 1 of 16 Data Inputs Typical	Original	SN74AS850A, SN74AS851B SDAS154A D2822, AS850A AS851B 600-mil D2822 SN74AS850A ALS138 SN74AS851B	PDF
HCF4034BM1 Abstract: HCF4034B HCF4034M013TR Text: HCF4034B 8 STAGE STATIC BIDIRECTIONAL PARALLEL/SERIAL INPUT OUTPUT BUS REGISTER • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ BIDIRECTIONAL PARALLEL DATA INPUT PARALLEL OR SERIAL INPUTS/PARALLEL OUTPUTS ASYNCHRONOUS OR SYNCHRONOUS PARALLEL DATA LOADING. PARALLEL DATA-INPUTS ENABLED ON ”A”	Original	HCF4034B 100nA JESD13B HCF4034B HCF4034BM1 HCF4034M013TR	PDF

d0422 Abstract: No abstract text available Text: Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp ADN2812 Data Sheet FEATURES GENERAL DESCRIPTION Serial data input: 12.3 Mb/s to 2.7 Gb/s Exceeds SONET requirements for jitter transfer/ generation/tolerance Quantizer sensitivity: 6 mV typical	Original	32-lead ADN2812 ADN2812 fo12ACPZ-RL ADN2812ACPZ-RL7 EVAL-ADN2812EBZ 12408-A d0422	PDF
MC100EL29 Abstract: No abstract text available Text: MC100EL29 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset Description The MC100EL29 is a dual master−slave flip flop. The device features fully differential Data and Clock inputs as well as outputs. Data enters the master latch when the clock is LOW and transfers to	Original	MC100EL29 MC100EL29 MC100EL29/D	PDF
Untitled Abstract: No abstract text available Text: O ctober 1990 PRELIMINARY ML2200 ML22Q8 *e,M icro Linear 12-Bit Plus Sign Data Acquisition Peripheral GENERAL DESCRIPTION FEATURES The ML2200 and ML2208 Data Acquisition Peripherals DAP are monolithic CMOS data acquisition subsystems. These data acquisition peripherals feature an input multiplexer, a	OCR Scan	ML2200 ML22Q8 12-Bit ML2208 ML2208 16-bit	PDF
HD64180 Abstract: 1N4148 1N5817 LT1027 LTC1290 LTC1290BC LTC1290BI LTC1290CC LTC1290CI LTC1290DC Text: LTC1290 single Chip 12-Bit Data Acquisition System TECHNOLOGY F€ATUR€S D€SCRIPTIO l • Software Programmable Features -Unipolar/Bipolar Conversion -4 Differential/8 Single Ended Inputs -MSB or LSB First Data Sequence -Variable Data Word Length -Power Shutdown	OCR Scan	50kHz LTC1290 12-Bit LTC1290 HD64180 1N4148 1N5817 LT1027 LTC1290BC LTC1290BI LTC1290CC LTC1290CI LTC1290DC	PDF
3044B-QIP80A Abstract: t-586 edc 16 cp LC89581 T496 T540 6 pin cdi T182 dlro Text: Ordering number: ENÍK3981 _ CMOSLSI _LC89581 sm iYO Preliminary Encoder for CD-ROM and CD-I Data i Overview Pin Assignment The LC89581 is an encoder for CD-ROM and CD-I data formats. It accepts 16-bit parallel input data, generates	OCR Scan	EN8S3981 LC89581 LC89581 16-bit 80-pin qqq000a 3044B-QIP80A t-586 edc 16 cp T496 T540 6 pin cdi T182 dlro	PDF
Untitled Abstract: No abstract text available Text: 4B2S771 □ D2 b 3 ö i 4 T 7D CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT Output Enable OE pin. The FIFOs accept 4-bit or 5-bit data at the data input (Do-D3,4 ). The stored data stack up on a firstin/first-out basis. A Shift Out (SO) signal causes the data at the next to last	OCR Scan	4B2S771 1O-S36-MT0 MS-013, D02b3Ã	PDF
Untitled Abstract: No abstract text available Text: LF9501 Program m able Line Buffer -EATURES DESCRIPTION □ 50 MHz Maximum Operating Frequency □ Programmable Buffer Length from 2 to 1281 Clock Cydes □ 10-bit Data Inputs and Outputs □ Data Delay and Data Recirculation Modes □ Supports Positive or Negative Edge	OCR Scan	LF9501 10-bit HSP9501 44-pin LF9501 10-bit LF9501JC40 LF9501JC31 LF9501JC25	PDF
Untitled Abstract: No abstract text available Text: FEATURES □ 30 MHz Data and Computation Rate □ Two 12 x 12-bit Multipliers with Individual Data Inputs □ Separate 16-bit Input Port for Cascading Devices □ Independent, User-Selectable 1-16 Clock Pipeline Delay for Each Data Input □ User-Selectable Rounding of	OCR Scan	12-bit 16-bit TMC2249 120-pin LF2249 LF2249 12-bit 24-bit	PDF
Untitled Abstract: No abstract text available Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Advance Information M C100LVEL29 M C100EL29 Dual Differential Data and Clock D Flip-Flop With Set and Reset The MC100LVEL29 is a dual m aster-slave flip flop. The device features fully differential Data and Clock inputs as well as outputs. The	OCR Scan	C100LVEL29 C100EL29 MC100LVEL29 MC100EL29 DL140) b3b75S5 BR1330	PDF
Untitled Abstract: No abstract text available Text: GD54/74LS157 QUADRUPLE 2-T0-1-LINE DATA SELECTORS/MULTIPLEXERS NON INVERTED DATA OUTPUTS Feature Pin Configuration • • Buffered Inputs and Outputs Common Strobe/Select input for all 4 circuits. INPUTS Vcc STROBE 4A Descriptions j _ 16 j _ j j 5 j _ This monolitic data selector/multiplexer contains	OCR Scan	GD54/74LS157	PDF

DATA INPUT Search Results

DATA INPUT Result Highlights (5)

DATA INPUT Price and Stock

Phoenix Contact RAD-ISM-900-DATA-BD-PLUS

DATA INPUT Datasheets Context Search

DM74S151

LV8153

DM74ALS153

Untitled

j16a

16 chanel input analog multiplexer

DDR200

K4H5

RDF-960

LS257

ALS157

ADSP21267

D2822

HCF4034BM1

d0422

MC100EL29

Untitled

HD64180

3044B-QIP80A

Untitled

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