W16A

Abstract: 54279DMQB 54279FMQB C1995 DM74 DM74279 DM74279N J16A N16E
Contextual Info: 54279 DM74279 Quad Set-Reset Latch General Description This device contains four independent set-reset type flipflops with one Q output each Connection Diagram Dual-In-Line Package TL F 9785 – 1 Order Number 54279DMQB 54279FMQB or DM74279N NS Package Number J16A N16E or W16A

W16A

Contextual Info: 16 Lead Ceramic Flatpack NS Package Number W16A All dimensions are in inches millimeters LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL

Contextual Info: DS26LV31T DS26LV31T 3V Enhanced CMOS Quad Differential Line Driver Literature Number: SNLS114B DS26LV31T 3V Enhanced CMOS Quad Differential Line Driver General Description The DS26LV31T is a high-speed quad differential CMOS driver that meets the requirements of both TIA/EIA-422-B

omap 1509

Contextual Info: DS26LS31C,DS26LS31M DS26LS31C/DS26LS31M Quad High Speed Differential Line Driver Literature Number: SNOSBK1B DS26LS31C/DS26LS31M Quad High Speed Differential Line Driver General Description Features The DS26LS31 is a quad differential line driver designed for

93L28FM

Abstract: 93L28 93L28DMQB 93L28FMQB C1995 J16A W16A F 93L28
Contextual Info: 93L28 Dual 8-Bit Shift Register General Description Features The 93L28 is a high speed serial storage element providing 16 bits of storage in the form of two 8-bit registers The multifunctional capability of this device is provided by several features 1 additional gating is provided at the input to

54AC253

Abstract: 54ACT253
Contextual Info: 54AC253 • 54ACT253 Dual 4-Input Multiplexer with TRI-STATE Outputs General Description The ’AC/’ACT253 is a dual 4-input multiplexer with TRI-STATE outputs. It can select two bits of data from four sources using common select inputs. The outputs may be individually switched to a high impedance state with a HIGH

54ac138

Abstract: AC138 54ACT138 ACT138
Contextual Info: 54AC138 • 54ACT138 1-of-8 Decoder/Demultiplexer General Description Features The ’AC/’ACT138 is a high-speed 1-of-8 decoder/ demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder

F 9324

Abstract: DM9324 9324DMQB 9324FMQB C1995 DM9324N J16A N16E W16A 9792
Contextual Info: 9324 DM9324 5-Bit Comparator General Description The 9324 expandable comparators provide comparison between two 5-bit words and give three outputs ‘‘less than’’ ‘‘greater than’’ and ‘‘equal to’’ A HIGH on the active LOW Enable Input forces all three outputs LOW

54ACT174

Abstract: 54AC174 AC174
Contextual Info: 54AC174 • 54ACT174 Hex D Flip-Flop with Master Reset General Description The ’AC/’ACT174 is a high-speed hex D flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition. The device has a

74F158APC

Abstract: 54F158ADM 54F158AFM 54F158ALM 74F158A 74F158ASC 74F158ASJ J16A N16E
Contextual Info: 54F 74F158A Quad 2-Input Multiplexer General Description Features The ’F158A is a high speed quad 2-input multiplexer It selects four bits of data from two sources using the common Select and Enable inputs The four outputs present the selected data in the inverted form The ’F158A can also generate any four of the 16 different functions of two variables

DM54LS174

Abstract: 54LS174 54LS174DMQB 54LS174FMQB 54LS175 DM54LS175 DM74LS174 DM74LS175 LS174 LS175
Contextual Info: 54LS174 DM54LS174 DM74LS174 54LS175 DM54LS175 DM74LS175 Hex Quad D Flip-Flops with Clear General Description Features These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic All have a direct clear input and the quad 175 versions feature complementary

93L38

Contextual Info: 93L38 93L38 8-Bit Multiple Port Register Literature Number: SNOS393A 93L38 8-Bit Multiple Port Register General Description Features The 93L38 is an 8-bit multiple port register designed for high speed random access memory applications where the ability to simultaneously read and write is desirable A common

Contextual Info: 9338,DM9338 9338/DM9338 8-Bit Multiple Port Register Literature Number: SNOS383A 9338 DM9338 8-Bit Multiple Port Register General Description The DM9338 is an 8-bit multiple port register designed for high speed random access memory applications where the

Contextual Info: 54F157A,74F157A 54F157A 74F157A Quad 2-Input Multiplexer Literature Number: SNOS155A 54F 74F157A Quad 2-Input Multiplexer General Description Features The ’F157A is a high-speed quad 2-input multiplexer Four bits of data from two sources can be selected using the

DS96F172

Abstract: DS96F174 EIA-422 EIA-485
Contextual Info: DS96F172M/DS96F174C/DS96F174M EIA-485/EIA-422 Quad Differential Drivers General Description Features The DS96F172 and the DS96F174 are high speed quad differential line drivers designed to meet EIA-485 Standards. The DS96F172 and the DS96F174 offer improved performance due to the use of L-FAST bipolar technology. The use

54LS368

Abstract: 54LS368A 54LS368ADMQB 54LS368AFMQB 54LS368ALMQB DM54LS368A DM54LS368AJ DM54LS368AW DM74LS368A DM74LS368AM
Contextual Info: 54LS368A DM54LS368A DM74LS368A Hex TRI-STATE Inverting Buffers General Description This device contains six independent gates each of which performs an inverting buffer function The outputs have the TRI-STATE feature When enabled the outputs exhibit the low impedance characteristics of a standard LS output with

54F174DM

Abstract: 54F174FM 54F174LM 74F174 74F174PC 74F174SC 74F174SJ J16A N16E f174
Contextual Info: 54F 74F174 Hex D Flip-Flop with Master Reset General Description Features The ’F174 is a high-speed hex D flip-flop The device is used primarily as a 6-bit edge-triggered storage register The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition The device has a

DS26C31TM

Abstract: DS26C31TN AM26LS31 DS26C31 DS26C31M DS26C31T DS26LS31
Contextual Info: DS26C31T/DS26C31M CMOS Quad TRI-STATE Differential Line Driver General Description The DS26C31 is a quad differential line driver designed for digital data transmission over balanced lines. The DS26C31T meets all the requirements of EIA standard RS-422 while retaining the low power characteristics of

LS279

Abstract: 54LS279 54LS279DMQB 54LS279FMQB 54LS279LMQB DM54LS279 DM54LS279J DM74LS279 DM74LS279M DM74LS279N
Contextual Info: 54LS279 DM54LS279 DM74LS279 Quad S-R Latches General Description The ’LS279 consists of four individual and independent SetReset Latches with active low inputs Two of the four latches have an additonal S input ANDed with the primary S input A low on any S input while the R input is high will be

TC5065

Abstract: 54F191DM 54F191FM 54F191LM 74F191 74F191PC 74F191SC 74F191SJ F191 J16A
Contextual Info: 54F 74F191 Up Down Binary Counter with Preset and Ripple Clock General Description Features The ’F191 is a reversible modulo-16 binary counter featuring synchronous counting and asynchronous presetting The preset feature allows the ’F191 to be used in programmable dividers The Count Enable input the Terminal Count

DS26LS32

Abstract: DS26LS32CM DS26LS33 DS26LS33A RS-423
Contextual Info: General Description Features The DS26LS32 and DS26LS32A are quad differential line receivers designed to meet the RS-422, RS-423 and Federal Standards 1020 and 1030 for balanced and unbalanced digital data transmission. The DS26LS32 and DS26LS32A have an input sensitivity of

AM26LS31

Abstract: DS26LS31 DS26LS31CM DS26LS31CN M16A N16E
Contextual Info: General Description Features The DS26LS31 is a quad differential line driver designed for digital data transmission over balanced lines. The DS26LS31 meets all the requirements of EIA Standard RS-422 and Federal Standard 1020. It is designed to provide unipolar differential drive to twisted-pair or parallel-wire

N16E

Abstract: W16A 9334DMQB 9334FMQB C1995 DM9334 DM9334J DM9334N J16A
Contextual Info: 9334 DM9334 8-Bit Addressable Latch General Description The DM9334 is a high speed 8-bit Addressable Latch designed for general purpose storage applications in digital systems It is a multifunctional device capable of storing single line data in eight addressable latches and being a oneof-eight decoder and demultiplexer with active level high

54LS257A

Abstract: 54LS258A DM54LS257B DM54LS258B DM74LS257B DM74LS258B LS157 LS158
Contextual Info: 54LS257A DM54LS257B DM74LS257B 54LS258A DM54LS258B DM74LS258B TRI-STATE Quad 2-Data Selectors Multiplexers General Description Features These Schottky-clamped high-performance multiplexers feature TRI-STATE outputs that can interface directly with data lines of bus-organized systems With all but one of the