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    ANIC

    Abstract: LS112 S125 DC74HC112
    Text: AVG Semiconductors _ DPP Technical Data DV74HCT112 Available Q2. 1995 DV74HC112 DV74HCT112 Dual J-K Flip-Flop with Set and Reset This device identical in pinout to the LS 1 12. Each flip-flop is negative-edge clocked and has active-low asynchronous Set


    OCR Scan     		DV74HCT112 LS112. DV74HC112 DV74HCT112 AVG-003 AVG-004 1-800-AVG-SEMI DC74HC112, ANIC LS112 S125 DC74HC112 PDF

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    Abstract: No abstract text available
    Text: AVG Semiconductors DDiT Technical Data DV74HCT112 Available Q2, 1995 DV74HC112 DV74HCT112 Dual J-K Flip-Flop with Set and Reset This device identical in pinout to the LS112. Each flip-flop is negative-edge clocked and has active-low asynchronous Set and Reset inputs.


    OCR Scan     		DV74HCT112 DV74HC112 DV74HCT112 LS112. AVG-003 AVG-004 1-800-AVG-SEMI DC74HC112, PDF