DDR 3 TSOP Search Results

DDR 3 TSOP Result Highlights (5)

Part	Manufacturer	Description
TPS51200TDB2	Texas Instruments	Sink/Source DDR Termination Regulator 0-
LP2995LQ/NOPB	Texas Instruments	DDR Termination Regulator 16-WQFN 0 to 125
TPS51200TDB1	Texas Instruments	Sink/Source DDR Termination Regulator 0-
TPS51100DGQG4	Texas Instruments	3A Source/Sink DDR terminator Regulator 10-MSOP-PowerPAD -40 to 85
TPS51100DGQ	Texas Instruments	3A Source/Sink DDR terminator Regulator 10-MSOP-PowerPAD -40 to 85

DDR 3 TSOP Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
AMD SEMPRON 3000 socket 754 DIAGRAM Abstract: diode SW1010 10USD TST1284A RS482M foxconn sw1010 ADOP15 88E8036 quanta Text: 1 2 3 4 5 6 PCB STACK UP AMD Athlon 64 & Sempron / RS482M / IXP400 LAYER 2 : VCC LAYER 3 : IN1 DDR 266,333,400MHz DDR-SODIMM1 P10 14.318MHz P3 A SYSTEM POWER 1.2V & VTT_DDR CPUCLK, CPUCLK# 754 Pins uPGA DDR-SODIMM2 LAYER 6 : BOT CPU THERMAL SENSOR GMT-781	Original	RS482M IXP400 400MHz GMT-781 318MHz CY28RS480/ ICS951412 MAX1544 16x16 OSC14M AMD SEMPRON 3000 socket 754 DIAGRAM diode SW1010 10USD TST1284A foxconn sw1010 ADOP15 88E8036 quanta	PDF
AMD SEMPRON 3000 socket 754 DIAGRAM Abstract: g10 t60 quanta PR137 foxconn conexant cx20468 ADOP15 cpu c644 100v 27p AMD Athlon 64 X2 4800 pin diagram PC126-1 Text: 1 2 3 4 5 6 PCB STACK UP AMD Athlon 64 & Sempron / RS480M / SB400 LAYER 2 : VCC LAYER 3 : IN1 DDR 266,333,400MHz DDR-SODIMM1 P10 14.318MHz P3 A SYSTEM POWER 1.2V & VTT_DDR CPUCLK, CPUCLK# 754 Pins uPGA DDR-SODIMM2 LAYER 6 : BOT CPU THERMAL SENSOR GMT-781	Original	RS480M SB400 400MHz GMT-781 318MHz CY28RS480/ ICS951412 MAX1544 16x16 OSC14M AMD SEMPRON 3000 socket 754 DIAGRAM g10 t60 quanta PR137 foxconn conexant cx20468 ADOP15 cpu c644 100v 27p AMD Athlon 64 X2 4800 pin diagram PC126-1	PDF
K4H560838C-TCB3 Abstract: K4H560838C-TCB0 DDR200 DDR266A DDR266B DDR333 Text: 256Mb C-die x4/8 DDR SDRAM DDR SDRAM Specification Version 0.5 - 1 - REV. 0.5 Nov. 3. 2001 256Mb C-die(x4/8) DDR SDRAM Revision History Version 0 (May, 2001) - First version for internal review of 256Mb C-die. Version 0.1 (July, 2001) - Updated target current spec(TSOP package base)	Original	256Mb K4H560838C-TCB3 K4H560838C-TCB0 DDR200 DDR266A DDR266B DDR333	PDF
M312L6523DZ3 Abstract: K4H561638J-LCCC k4h561638j K4H641638N k4h560438j K4H560838J-LCCC DDR266 DDR333 DDR400 K4H560438H Text: General Information DDR SDRAM DDR SDRAM Product Guide December 2007 Memory Division December 2007 General Information DDR SDRAM A. DDR SDRAM Component Ordering Information 1 2 3 4 5 6 7 8 9 10 11 K 4 H X X X X X X X - X X X X Speed SAMSUNG Memory DRAM Temperature & Power	Original	128Mb, 4K/64ms 256Mb, 60Ball 512Mb) 00MAX M312L6523DZ3 K4H561638J-LCCC k4h561638j K4H641638N k4h560438j K4H560838J-LCCC DDR266 DDR333 DDR400 K4H560438H	PDF
1993 synchronous dram jedec Abstract: dram ddr 1997 1993 SDRAM Text: NEW PRODUCTS 3 128-Mbit DDR SYNCHRONOUS DRAM Yoshitomo Asakura Photo 1 µPD45128842 128Mbit DDR SDRAM NEC has newly developed a world-leading 128-Mb double data rate DDR synchronous DRAM (SDRAM) product (Photo 1) which comes in three configurations. Development Background	Original	128-Mbit PD45128842 128Mbit 128-Mb PD45D128442 Con36 1993 synchronous dram jedec dram ddr 1997 1993 SDRAM	PDF
K4H510638C-TCB0 Abstract: DDR266A DDR266B DDR333 K4H510638C-TCA0 K4H510638C-TCA2 K4H510638C-TCB3 DDR200 Text: Stacked 512Mb x4 DDR SDRAM DDR SDRAM Specification Version 0.1 - 1 - REV. 0.1 Nov. 3. 2001 Stacked 512Mb(x4) DDR SDRAM Revision History Version 0 (October, 2001) - First version for internal review Version 0.1(November,2001) - Deleted tHZ/tLZ of DQS - 2 -	Original	512Mb 166Mhz 133Mhz 100Mhz 128Mx4 K4H510638C-TCB3 K4H510638C-TCA2 K4H510638C-TCB0 DDR266A DDR266B DDR333 K4H510638C-TCA0 K4H510638C-TCA2 K4H510638C-TCB3 DDR200	PDF
K4H510838M-TCB0 Abstract: DDR200 DDR266A DDR266B K4H510438M-TCA2 K4H510438M-TCB0 K4H510438M-TLA2 K4H510438M-TLB0 K4H510838M-TCA2 K4H510838M-TLA2 Text: 512Mb DDR SDRAM Preliminary DDR SDRAM Specification Version 0.5 - 1 - REV. 0.5 Nov.3. 2001 512Mb DDR SDRAM Preliminary Revision History Version 0.0 May, 2000 - Prototype 512Mb specification - DC current is "TBD" and will be defined from M-die Version 0.1(Apr,2001)	Original	512Mb K4H510838M-TCB0 DDR200 DDR266A DDR266B K4H510438M-TCA2 K4H510438M-TCB0 K4H510438M-TLA2 K4H510438M-TLB0 K4H510838M-TCA2 K4H510838M-TLA2	PDF
DDR200 Abstract: DDR266A DDR266B K4H281638D-TCA2 K4H281638D-TCB0 K4H281638D-TLA2 K4H281638D-TLB0 K4H281638D-TCB3 Text: 128Mb D-die x16 DDR SDRAM DDR SDRAM Specification Version 0.3 - 1 - REV. 0.3 Nov. 3. 2001 128Mb D-die(x16) DDR SDRAM Revision History Version 0 (July, 2001) - First version for internal review Version 0.1 (September, 2001) - Changed spec to preliminary version	Original	128Mb DDR200 DDR266A DDR266B K4H281638D-TCA2 K4H281638D-TCB0 K4H281638D-TLA2 K4H281638D-TLB0 K4H281638D-TCB3	PDF
Untitled Abstract: No abstract text available Text: NT5DS64M8DS NT5DS32M16DS 512Mb DDR SDRAM Preliminary Edition Feature CAS Latency Frequency z 2KB page size for all configurations. DDR-333 DDR400 DDR500 -6K/-6KI -5T/-5TI -4T 2.5-3-3 3-3-3 3-4-4 CL=2 266 266 - CL=2.5 333 333 333 CL=3 333 400 500 Speed Sorts	Original	NT5DS64M8DS NT5DS32M16DS 512Mb DDR-333 DDR400 DDR500 DDR-333) DDR-400/500)	PDF
NT5DS16M16DS-6K Abstract: NT5DS16M16DS Text: NT5DS32M8DS NT5DS16M16DS 256Mb DDR SDRAM Feature CAS Latency Frequency DDR-333 DDR400 DDR500 -6K/-6KI -5T/-5TI -4C 2.5-3-3 3-3-3 3-4-4 CL=2 266 266 - CL=2.5 333 333 333 CL=3 333 400 500 Speed Sorts CL-tRCD-tRP Speed z z 2KB page size for all configurations.	Original	NT5DS32M8DS NT5DS16M16DS 256Mb DDR-333 DDR400 DDR500 DDR-333) DDR-400/500) NT5DS16M16DS-6K NT5DS16M16DS	PDF
NT5DS16M16DS Abstract: 256mbddrsdram Text: NT5DS32M8DS NT5DS16M16DS 256Mb DDR SDRAM Feature CAS Latency Frequency DDR-333 DDR400 DDR500 -6K/-6KI -5T/-5TI -4C 2.5-3-3 3-3-3 3-4-4 CL=2 266 266 - CL=2.5 333 333 333 CL=3 333 400 500 Speed Sorts CL-tRCD-tRP Speed z z 2KB page size for all configurations.	Original	NT5DS32M8DS NT5DS16M16DS 256Mb DDR-333 DDR400 DDR500 DDR-333) DDR-400/500) NT5DS16M16DS 256mbddrsdram	PDF
Untitled Abstract: No abstract text available Text: 256Mb DDR SDRAM DDR SDRAM Specification Version 1.0 - 1 - REV. 1.0 Nov. 3. 2001 256Mb DDR SDRAM Revision History Version 0 May, 2000 - First version for internal review of 256Mb B-die. Version 0.1(July,2000) - Added DC target spec values - Deleted tDAL in AC parameter X	Original	256Mb	PDF
NT5DS8M16HS Abstract: No abstract text available Text: NT5DS8M16HS 128Mb DDR SDRAM Feature z 2KB page size for all configurations. CAS Latency Frequency z DQS is edge-aligned with data for reads and is DDR-333 DDR400 -6K/-6KI -5T/-5TI 2.5-3-3 3-3-3 CL2 266 266 CL2.5 333 333 CL3 333 400 Speed Sorts CL-tRCD-tRP	Original	NT5DS8M16HS 128Mb DDR-333 DDR400 DDR-333) DDR-400) NT5DS8M16HS	PDF
NT5DS32M16DS Abstract: NT5DS64M8DS NT5DS32M16 Text: NT5DS64M8DS NT5DS32M16DS 512Mb DDR SDRAM Preliminary Edition Feature CAS Latency Frequency z 2KB page size for all configurations. DDR-333 DDR400 DDR500 -6K/-6KI -5T/-5TI -4T 2.5-3-3 3-3-3 3-4-4 CL=2 266 266 - CL=2.5 333 333 - CL=3	Original	NT5DS64M8DS NT5DS32M16DS 512Mb DDR-333 DDR400 DDR500 DDR-333) DDR-400/500) NT5DS32M16DS NT5DS32M16	PDF

K4H280838C-TCB0 Abstract: DDR200 DDR266A DDR266B DDR333 samsung xsr samsung 128Mb DDR SDRAM 0.3 1998 Text: 128Mb C-die x4/8 DDR SDRAM DDR SDRAM Specification Version 0.7 - 1 - REV. 0.7 Nov.3. 2001 128Mb C-die(x4/8) DDR SDRAM 128Mb C-die Revision History Version 0 (Jan, 2001) - First version for internal review Version 0.1(Feb, 2001) - Changed spec to preliminary version.	Original	128Mb K4H280838C-TCB0 DDR200 DDR266A DDR266B DDR333 samsung xsr samsung 128Mb DDR SDRAM 0.3 1998	PDF
Untitled Abstract: No abstract text available Text: N2DS25680DS N2DS25616DS Preliminary 256Mb DDR SDRAM  Feature CAS Latency Frequency DDR-333 center-aligned with data for WRITEs DDR400 Speed Sorts -5T 2.5-3-3 3-3-3 CL=2 266 266 CL=2.5 333 333 CL=3 333 400 CL-tRCD-tRP Speed  Units -6K  Differential clock inputs CK and 	Original	N2DS25680DS N2DS25616DS 256Mb DDR-333 DDR400 DDR-333) 400mil;	PDF
Untitled Abstract: No abstract text available Text: Stacked 512Mb x4 DDR SDRAM DDR SDRAM Specification Version 0.4 - 1 - REV. 0.4 Nov. 3. 2001 Stacked 512Mb(x4) DDR SDRAM Revision History Version 0 (March, 2001) - First version for internal review Version 0.1(March,2001) - Changed from supporting QFC function to not supporting QFC function(Deleted all QFC function supported)	Original	512Mb	PDF
16x16 LED Matrix Abstract: 68x2 quanta foxconn RS480M TST1284A cpu c644 100v 27p AMD Athlon 64 X2 4800 pin diagram FB147 conexant cx20493 reference design Text: 1 2 3 4 5 6 PCB STACK UP AMD Athlon 64 & Sempron / RS480M / SB400 LAYER 2 : VCC A DDR 266,333,400MHz DDR-SODIMM1 GMT-781 P10 14.318MHz P3 A SYSTEM POWER 1.2V & VTT_DDR P35 CPUCLK, CPUCLK# 754 Pins uPGA DDR-SODIMM2 LAYER 6 : BOT CPU THERMAL SENSOR AMD Athlon 64 &	Original	RS480M SB400 400MHz GMT-781 318MHz CY28RS480/ ICS951412 16x16 MAX1544 MAX1999 16x16 LED Matrix 68x2 quanta foxconn TST1284A cpu c644 100v 27p AMD Athlon 64 X2 4800 pin diagram FB147 conexant cx20493 reference design	PDF
58-Rev Abstract: nt5ds64m8 Text: NT5DS64M8DS NT5DS32M16DS 512Mb DDR SDRAM Feature CAS Latency Frequency z 2KB page size for all configurations. DDR-333 DDR400 DDR500 -6K/-6KI -5T/-5TI -4T 2.5-3-3 3-3-3 3-4-4 CL=2 266 266 - CL=2.5 333 333 333 CL=3 333 400 500 Speed Sorts	Original	NT5DS64M8DS NT5DS32M16DS 512Mb DDR-333 DDR400 DDR500 DDR-333) DDR-400/500) 58-Rev nt5ds64m8	PDF
Untitled Abstract: No abstract text available Text: NT5DS64M8DS NT5DS32M16DS 512Mb DDR SDRAM Feature CAS Latency Frequency z 2KB page size for all configurations. DDR-333 DDR400 DDR500 -6K/-6KI -5T/-5TI -4T 2.5-3-3 3-3-3 3-4-4 CL=2 266 266 - CL=2.5 333 333 333 CL=3 333 400 500 Speed Sorts	Original	NT5DS64M8DS NT5DS32M16DS 512Mb DDR-333 DDR400 DDR500 DDR-333) DDR-400/500)	PDF
Untitled Abstract: No abstract text available Text: NT5DS64M8DS NT5DS32M16DS 512Mb DDR SDRAM Feature CAS Latency Frequency z 2KB page size for all configurations. DDR-333 DDR400 DDR500 -6K/-6KI -5T/-5TI -4T 2.5-3-3 3-3-3 3-4-4 CL=2 266 266 - CL=2.5 333 333 333 CL=3 333 400 500 Speed Sorts	Original	NT5DS64M8DS NT5DS32M16DS 512Mb DDR-333 DDR400 DDR500 DDR-333) DDR-400/500)	PDF
Untitled Abstract: No abstract text available Text: NT5DS64M8DS NT5DS32M16DS 512Mb DDR SDRAM Feature CAS Latency Frequency  2KB page size for all configurations. DDR-333 DDR400 DDR500 -6K/-6KI -5T/-5TI -4T 2.5-3-3 3-3-3 3-4-4 CL=2 266 266 - CL=2.5 333 333 333 CL=3 333 400 500 Speed Sorts Units  DQS is edge-aligned with data for reads and is	Original	NT5DS64M8DS NT5DS32M16DS 512Mb DDR-333 DDR400 DDR500 DDR-333) DDR-400/500)	PDF
Untitled Abstract: No abstract text available Text: NT5DS64M8DS NT5DS32M16DS 512Mb DDR SDRAM Feature CAS Latency Frequency  2KB page size for all configurations. DDR-333 DDR400 DDR500 -6K/-6KI -5T/-5TI -4T 2.5-3-3 3-3-3 3-4-4 CL=2 266 266 - CL=2.5 333 333 333 CL=3 333 400 500 Speed Sorts Units  DQS is edge-aligned with data for reads and is	Original	NT5DS64M8DS NT5DS32M16DS 512Mb DDR-333 DDR400 DDR500	PDF
NT5DS32M16 Abstract: No abstract text available Text: NT5DS64M8DS NT5DS32M16DS 512Mb DDR SDRAM Feature CAS Latency Frequency z 2KB page size for all configurations. DDR-333 DDR400 DDR500 -6K/-6KI -5T/-5TI -4T 2.5-3-3 3-3-3 3-4-4 CL=2 266 266 - CL=2.5 333 333 333 CL=3 333 400 500 Speed Sorts	Original	NT5DS64M8DS NT5DS32M16DS 512Mb DDR-333 DDR400 DDR500 DDR-333) DDR-400/500) NT5DS32M16	PDF

DDR 3 TSOP Search Results

DDR 3 TSOP Result Highlights (5)

DDR 3 TSOP Datasheets Context Search

AMD SEMPRON 3000 socket 754 DIAGRAM

AMD SEMPRON 3000 socket 754 DIAGRAM

K4H560838C-TCB3

M312L6523DZ3

1993 synchronous dram jedec

K4H510638C-TCB0

K4H510838M-TCB0

DDR200

Untitled

NT5DS16M16DS-6K

NT5DS16M16DS

Untitled

NT5DS8M16HS

NT5DS32M16DS

K4H280838C-TCB0

Untitled

Untitled

16x16 LED Matrix

58-Rev

Untitled

Untitled

Untitled

Untitled

NT5DS32M16