DM74LS5 Search Results

DM74LS503

Abstract: DM74LS503N MS-001 N16E
Contextual Info: Revised March 2000 DM74LS503 8-Bit Successive Approximation Register with Expansion Control General Description Features The DM74LS503 register has an active LOW Enable (E) input that is used in cascading two or more packages for longer word lengths. A HIGH signal on E, after a START

74ls503

Abstract: 74ls50
Contextual Info: S E M IC O N D U C T O R t DM74LS503 8-Bit Successive Approximation Register with Expansion Control General Description Features The ’LS503 register is basically the sam e as the ’LS502 e x­ cept that it has an active LO W Enable (E) input th a t is used

DM74LS373

Abstract: DM74LS533 DM74LS533N DM74LS533WM MS-001 MS-013
Contextual Info: Revised March 2000 DM74LS533 Octal Transparent Latch with 3-STATE Outputs General Description Features The DM74LS533 consists of eight latches with 3-STATE outputs for bus organized system applications. The flipflops appear transparent to the data when Latch Enable

54LS51

Abstract: 54LS51DMQB 54LS51FMQB 54LS51LMQB DM74LS51M DM74LS51N E20A J14A M14A N14A
Contextual Info: National é l â Semiconductor 54LS51/DM74LS51 Dual 2-Wide 2-Input, 2-Wide 3-Input AND-OR-INVERT Gates General Description This device contains two independent combinations of gales each of which performs the logic AND-OR-INVERT function. Each package contains one 2-wide 2-input and

54LS51DMQB

Abstract: 54LS51FMQB 54LS51LMQB DM74LS51M DM74LS51N E20A J14A M14A N14A
Contextual Info: , June 1989 54LS51/DM74LS51 Dual 2-Wide 2-Input, 2-Wide 3-Input AND-OR-INVERT Gates General Description This device contains two independent combinations of gates each of which performs the logic AND-OR-INVERT function. Each package contains one 2-wide 2-input and

DM74LS540N

Abstract: ON semiconductor LS240 C1995 DM74LS540 DM74LS540WM LS240 LS540 3B225
Contextual Info: DM74LS540 Octal Buffer Line Driver with TRI-STATE Outputs General Description Features The ‘LS540 is similar in function to the ’LS240 except that the inputs and outputs are on opposite sides of the package see Connection Diagram This pinout arrangement makes

54LS55DMQB

Abstract: 54LS55FMQB DM74LS55M DM74LS55N J14A M14A N14A W14B
Contextual Info: LS55 National Semiconductor 54LS55/DM74LS55 2-Wide, 4-Input AOI Gate General Description This device contains a combination of AND-OR-INVERT functions. The internai gates are configured as two, four-input AND gates with their outputs connected to a two-input NOR gate.

101902

Abstract: 54LS503DMQB 54LS503FMQB DM74LS503N J16A M16B VCC71
Contextual Info: LS503 CT1 National Juâ Semiconductor 54LS503/DM74LS503 8-Bit Successive Approximation Register with Expansion Control General Description Features The 'LS503 register is basically the same as the ’LS502 except that it has an active LOW Enable (E) input that is

.5J1

Abstract: 54LS54DMQB 54LS54FMQB DM74LS54M DM74LS54N J14A M14A N14A W14B
Contextual Info: LS54 2 3 National Semiconductor 54LS54/DM74LS54 4-WIDE, 2-Input AND-OR-INVERT Gate General Description This device contains a combination of four, two input AND gates whose outputs are connected to a four input NOR Gate. Connection Diagram Dual-ln-Line Package

Contextual Info: June 1992 DM74LS573 Octal D Latch with TRI-STATE Outputs General Description Features The ’LS573 is a high speed octal latch with buffered com­ mon Latch Enable LE and buffered common Output En­ able (OE) inputs. • Inputs and outputs on opposite sides of package

762T

Abstract: DM74LS
Contextual Info: & a t i o n a l S e m i c o n d u c t o r DM54LS54/DM74LS54 4-WIDE, 2-Input AND-OR-INVERT Gate G eneral Description This device contains a combination of tour, two input AND gates whose outputs are connected to a four input NOR Gate. Connection Diagram Dual-ln-Line Package

ls373

Contextual Info: LS533 National Semiconductor DM74LS533 Octal Transparent Latch with TRI-STATE Outputs General Description The 'LS533 consists of eight latches with TRI-STATE out­ puts for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable LE is

Contextual Info: February 1992 Semiconductor & DM74LS564 Octal D-Type Flip-Flop with TRI-STATE Outputs General Description Features The ’LS564 is a high speed low power octal flip-flop with a buffered common Clock CP and a buffered common Out­ put Enable (OE). The information presented to the D inputs

successive approximation

Abstract: DM54LS502 DM54LS502J DM54LS502W DM74LS502 DM74LS502N DM74LS502WM J16A M16B N16E
Contextual Info: DM54LS502 DM74LS502 8-Bit Successive Approximation Register General Description The LS502 is an 8-bit register with the interstage logic necessary to perform serial-to-parallel conversion and provide an active LOW Conversion Complete CC signal coincident

Contextual Info: w w w .fa irc h ild s e m i.c o m DM74LS51 Dual 2-Wide 2-Input, 2-Wide 3-Input AND-OR-INVERT Gates DC LU > ?w DC c \j O Û I m a w cn g LU ca Z iS c O o > z T cn O ? CD o < « S z !3 =< ^ Q •'f I co Q 3 Q. C 5 Q. ■ CO 0) »o S S m Û !/) i- _l IO «^

74LS53

Abstract: 74LS533W 74LS533N
Contextual Info: R C H U - P S E M IC O N D U C T O R tm DM74LS533 Octal Transparent Latch with 3-STATE Outputs General Description The ’LS533 consists of eight latches w ith 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data w hen Latch Enable LE is HIGH.

Contextual Info: I R C H I L D S E M IC O N D U C T O R T M DM74LS573 Octal D Latch with 3-STATE Outputs General Description Features The ’LS573 is a high speed octal latch with buffered com m on Latch Enable LE and buffered com m on O utput Enable (OE) inputs. • Inputs and outputs on opposite sides of package

54LS55DMQB

Abstract: 54LS55FMQB DM74LS55N J14A M14A N14A W14B
Contextual Info: NATIONAL SEflICOND -CLOGIO B1E D National Semiconductor bsoiias GGb^aas a 7 ' ’ef 3 - i 5 ~0 O ' 54LS55/DM74LS55 2-Wide, 4-Input AOI Gate General Description This device contains a combination of AND-OR-INVERT functions. The internal gates are configured as two,

DM74LS503

Abstract: DM54LS503J DM54LS503W DM74LS503N DM74LS503WM J16A
Contextual Info: DM74LS503 8-Bit Successive Approximation Register with Expansion Control General Description Features The ’LS503 register is basically the same as the ’LS502 except that it has an active LOW Enable (E) input that is used in cascading two or more packages for longer word lengths.

Contextual Info: June 1989 54LS51/DM74LS51 Dual 2-Wide 2-Input, 2-Wide 3-Input AND-OR-INVERT Gates General Description This device contains two independent combinations of gates each of which performs the logic AND-OR-INVERT function. Each package contains one 2-wide 2-input and

Contextual Info: January 1992 DM74LS534 Octal D-Type Flip-Flop With TRI-STATE Outputs General Description The ’LS534 is a high speed, low power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and TRI­ STATE outputs for bus oriented applications. A buffered

res 7112

Abstract: DM54LS503J DM54LS503W DM74LS503 DM74LS503N DM74LS503WM M16B N16E W16A
Contextual Info: SEMICONDUCTOR t DM74LS503 8-Bit Successive Approximation Register with Expansion Control General Description Features T h e ’L S 5 0 3 re g is te r is b a s ic a lly th e s a m e as th e ’L S 5 0 2 e x ­ ce p t th a t it h as an a c tiv e L O W E n a b le (E) in p u t th a t is us e d

DM74LS574N

Abstract: DM74LS574 DM74LS574WM LS374
Contextual Info: S E M IC O N D U C T O R tm DM74LS574 Octal D Flip-Flop with 3- STATE Outputs General Description This device is functionally identical to the ’LS374 except for the pinouts. The ’LS574 is a high speed low power octal flip-flop with a buffered c o m m on C lock CP and a buffered com m on O ut­

Contextual Info: DM54LS502 DM74LS502 8-Bit Successive Approximation Register General Description The LS502 is an 8-bit register with the interstage logic necessary to perform serial-to-parallel conversion and provide an active LOW Conversion Complete CC signal coincident