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    DN74LS11 Search Results

    DN74LS11 Datasheets (16)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    DN74LS112D Panasonic Dual J-K Negative Edge Triggered Flip-Flops (with set and reset) Scan PDF
    DN74LS112N Panasonic Dual J-K Negative Edge Triggered Flip-Flops (with Set and Reset) Scan PDF
    DN74LS112P Panasonic Dual J-K Negative Edge Triggered Flip-Flops (with set and reset) Scan PDF
    DN74LS112S Panasonic Dual J-K Negative Edge Triggered Flip-Flops (with Set and Reset) Scan PDF
    DN74LS113D Panasonic Dual J-K Negative Edge-Triggered Flip-Flops (with set) Scan PDF
    DN74LS113N Panasonic Dual J-K Negative Edge-Triggered Flip-Flops (with set) Scan PDF
    DN74LS113P Panasonic Dual J-K Negative Edge-Triggered Flip-Flops (with set) Scan PDF
    DN74LS113S Panasonic Dual J-K Negative Edge-Triggered Flip-Flops (with set) Scan PDF
    DN74LS114D Panasonic Dual J-K Negative Edge Triggered Flip-Flops (with Set, Common Reset, and Common Clock) Scan PDF
    DN74LS114N Panasonic Dual J-K Negative Edge Triggered Flip-Flops Scan PDF
    DN74LS114P Panasonic Dual J-K Negative Edge Triggered Flip-Flops (with Set, Common Reset, and Common Clock) Scan PDF
    DN74LS114S Panasonic Dual J-K Negative Edge Triggered Flip-Flops Scan PDF
    DN74LS11N Panasonic Triple 3-Input Positive AND Gates Scan PDF
    DN74LS11N Panasonic Triple 3-input Positive AND Gates Scan PDF
    DN74LS11S Panasonic Triple 3-Input Positive AND Gates Scan PDF
    DN74LS11S Panasonic Triple 3-input Positive AND Gates Scan PDF

    DN74LS11 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    MN1873287

    Abstract: an6512n 2sk3190 MN171202 mn158413 mn15142 mn187164 mn6740 AN7210 MN15283
    Text: Maintenance and Discontinued Types <Maintenance Types> Maintenance and Discontinued Types This product is not dealt with anymore. Customers dealing with this product conventionally may contact our sales division in the case of ambiguity. <Discontinued Types>


    Original
    MN101C01C MN15224 MN101C01D MN15226 MN101C027 MN15261 MN101C03A MN101C38A MN15263 MN101C06D MN1873287 an6512n 2sk3190 MN171202 mn158413 mn15142 mn187164 mn6740 AN7210 MN15283 PDF

    sr flip flop

    Abstract: DN74LS113 MA161
    Text: DN74LS113 LS TTL DN74LS Series D N 7 4 L S 1 1 3 ^ 7 ^ U S 3 Dual J-K Negative Edge-Triggered F lip -F lo p s with Set) • Description P-l D N74LS113 contains tw o negative-edge triggered J-K flip­ flop circuits, each w ith independent clock-CP, J, K, and


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    DN74LS DN74LS113 DN74LS113 14-pin S0-140) MA161. trS15ns, sr flip flop MA161 PDF

    Untitled

    Abstract: No abstract text available
    Text: LS TTL DN74LS Series DN74LS11 DN74LS11 D^74LS11 Triple 3-input P ositive AND Gates • Description P-1 D N 74L S 11 contains three 3-input positive isolation AND gate circuits. I Features • Low pow er consum ption P d = 13mW typical • High speed ( t pii = 9ns typical)


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    DN74LS DN74LS11 DN74LS11 74LS11 14-pin SO-14D) MA161. PDF

    Untitled

    Abstract: No abstract text available
    Text: I LS TTL DN74LS Series DN74LS113 DN74LS113 Dual J-K Negative Edge-Triggered Flip-Flops with Set I Description P-1 DN74LS113 contains two negative-edge triggered J-K flipflop circuits, each with independent clock-CP, J, K, and direct-coupled set input terminals.


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    DN74LS DN74LS113 DN74LS113 14-pin SO-14D) MA161. S15ns, PDF

    Untitled

    Abstract: No abstract text available
    Text: I LS TTL DN74LS Series DN74LS11 DN74LS11 T riple 3 -input P o sitiv e AND Gates • Description P-1 D N 7 4 L S 1 1 con tain s three 3-in put p ositive isolation A N D gate circuits. ■ Features • • • • L ow p o w er co n su m p tio n P d = 13mW ty p ica l


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    DN74LSSÃ dN74LSii DN74LS11 14-pin SO-14D) DN74LS MA161. PDF

    DN74LS112

    Abstract: MA161
    Text: LS TTL DN74LS Series DN74LS112 DN74LS112 Dual J-K Negative Edge-Triggered F lip-F lops with S et and Reset • P-2 Description D N 7 4 L S 1 1 2 c o n ta in s tw o negative-edge trig g ered J-K flip ­ flo p c irc u its, e ac h w ith in d e p e n d e n t clock-C P , J , K , an d


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    DN74LS DN74LS112 DN74LS112 16-ptn 16-pin S0-160) MA161 PDF

    DN74LS11

    Abstract: MA161
    Text: I LS TTL DN74LS Series DN74LS11 DN74LS11 T riple 3 -input P o sitiv e AND Gates • Description P-1 D N 7 4 L S 1 1 con tain s three 3-in put p ositive isolation A N D gate circuits. ■ Features • • • • L ow p o w er co n su m p tio n P d = 13mW ty p ica l


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    DN74LSSeries dN74LSii DN74LS11 DN74LS11 14-pin SO-14D) DN74LS MA161. MA161 PDF

    ma161

    Abstract: No abstract text available
    Text: LS TTL DN74LS Series DN74LS112 DN74LS112 Dual J-K Negative Edge-Triggered F lip-F lops with S et and Reset • P-2 Description D N74LS112 contains two negative-edge triggered J-K flip­ flop circuits, each w ith independent clock-CP, J , K, and direct-coupled set and reset in p u t term inals.


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    DN74LS DN74LS112 16-ptn 16-pin S0-160) ma161 PDF

    Untitled

    Abstract: No abstract text available
    Text: LS TTL DN74LS Series DN74LS114 DN74LS114 ivj'7q_ uSiiq- Dual J-K Negative Edge-Triggered F lip-F lops with Set,Common Reset and Common Clock • Description P-1 D N 74L S 1I4 contains tw o negative-edge triggered J-K flipflop circuits w ith com m on clock-CP and direct-coupled reset


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    DN74LS DN74LS114 PDF

    DN74LS114

    Abstract: MA161
    Text: LS TTL DN74LS Series DN74LS114 DN74LS114 Dual J-K Negative Edge-Triggered F lip -F lop s with Set, Common Reset and Common Clock • Description D N 74L S114 contains two negative-edge triggered J-K flip­ flop circuits w ith com m on clock-CP and direct-coupled reset


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    DN74LS DN74LS114 DN74LS114 14-pin SO-14D) MA161 PDF

    DN74LS112

    Abstract: MA161
    Text: LS T T L DN74LS Series DN74LS112 DN74LS112 107^ Dual J-K Negative Edge-Triggered Flip-F lops with S et and Reset I Description P -2 DN74LS112 contains two negative-edge triggered J-K flip­ flop circuits, each with independent clock-CP, J, K , and direct-coupled set and reset input terminals.


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    DN74LS DN74LS112 DN74LS112 16-pm 16-pin SO-16D) MA161 PDF

    Untitled

    Abstract: No abstract text available
    Text: I DN74LS11 L S T T L DN74LS Series DN74LS11 Triple 3 -input P ositive AND Gates P-1 • Description D N 7 4 L S 1 1 c o n ta in s th re e 3 -in p u t p o sitiv e is o la tio n A N D gate circ u its. ■ Features • L ow p o w e r c o n s u m p tio n P d = 13m W ty p ic a l


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    DN74LS DN74LS11 14-pin SO-14D) PDF

    Untitled

    Abstract: No abstract text available
    Text: LS TTL DN74LS Series D N 7 4 LS1 1 2 DN74LS112 i0 7 ^ IS ¡ ¡ ^ Dual J-K Negative Edge-Triggered Flip-Flops with Set and Reset H Description P -2 DN 74LS112 contains two negative-edge triggered J-K flipflop circuits, each w ith independent clock-CP, J, K, and


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    DN74LS DN74LS112 74LS112 PDF

    Untitled

    Abstract: No abstract text available
    Text: LS TTL DN74LS Series DN74LS114 DN74LS114 Dual J-K Negative Edge-Triggered F lip-F lops with Set, Common Reset and Common Clock • Description DN74LS114 contains two negative-edge triggered J-K flipflop circuits with common clock-CP and direct-coupled reset


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    DN74LS DN74LS114 DN74LS114 PDF

    74LS11 pin configuration

    Abstract: TTL 74LS11 74LS11 TTL 400M 74LS11 DN74LS11 MA161 50nd
    Text: LS T T L DN74LS Series DN74LS11 DN74LS11 D^74LS11 Triple 3-input Positive AND Gates P-1 • Description DN74LS11 contains three 3-input positive isolation AND gate circuits. ■ Features • • • • Low pow er consum ption Pd = 13mW typical High speed (tpd = 9ns typical)


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    DN74LS DN74LS11 DN74LS11 74LS11 14-pin SO-14D) MA161. 74LS11 pin configuration TTL 74LS11 74LS11 TTL 400M 74LS11 MA161 50nd PDF

    DN74LS113

    Abstract: MA161 100 mhz trigger generator 0n74
    Text: I DN74LS113 LS TTL DN74LS Series D N 74LS 113 Dual J-K Negative Edge-Triggered F lip -F lop s with Set I Description P-1 DN74LS113 contains two negative-edge triggered J-K flip­ flop circuits, each with independent clock-CP, J, K, and direct-coupled set input terminals.


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    0N74LS DN74LS113 DN74LS113 14-pin SO-14D) trS15ns. MA161 100 mhz trigger generator 0n74 PDF

    JK flip flop IC

    Abstract: No abstract text available
    Text: LS TTL DN74LS Series DN74LS113 DN74LS113 l^7^iS 3 Dual J-K Negative Edge-Triggered Flip-Flops with Set) • Description DN74LS113 contains two negative-edge triggered J-K flipflop circuits, each with independent clock-CP, J, K, and direct-coupled set input terminals.


    OCR Scan
    DN74LS DN74LS113 DN74LS113 14-pin SO-14D) MA161. JK flip flop IC PDF

    Untitled

    Abstract: No abstract text available
    Text: LS TTL DN74LS Series DN74LS112 D N 7 4 L S 1 1 2 Dual J-K Negative Edge-Triggered Flip-Flops with Set and Reset • Description P-2 DN74LS112 contains two negative-edge triggered J-K flipflop circuits, each with independent clock-CP, J, K, and direct-coupled set and reset input terminals.


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    DN74LS DN74LS112 DN74LS112 16-pin PDF

    an6512n

    Abstract: mn1225 MN1280 mn6520 MN6130 MN1201A MN6147C MN12C261D MN12C201D MN3107
    Text: <Maintenance Types> This product is not dealt with anymore. Customers dealing with this product conventionally may contact our sales division in the case of ambiguity. <Scrapped Types> Apart from the inquiry concerning repair parts, we will refrain from taking any counteraction.


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    MN115P MN116P MN1201A MN1201M MN1201S MN1202M MN1204A MN1204B MN1204E MN1204F an6512n mn1225 MN1280 mn6520 MN6130 MN6147C MN12C261D MN12C201D MN3107 PDF

    MN1280

    Abstract: AN6512 MN15814 MN15245 2Sb1163a mn158413 AN7210 AN7226 MN15287 MN15283
    Text: pes H Maintenance • mos LS Is Type No. Alternative ^ype No. Alternative Type No. - MN6040Z — - MN6049 MN3726FE/AE MN4520B/S MN4521 B/S - — MN3726AE MN4522B/S - MN6063 MN6063A - MN4526B/S - MN6064 - - MN4528B/S — - MN4532B/S MN6064R/S MN61074


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    MN1380 MN13801 MN13802 MN1381 MN13811 MN13812 MN1382 MN13821 MN13822 MN1544 MN1280 AN6512 MN15814 MN15245 2Sb1163a mn158413 AN7210 AN7226 MN15287 MN15283 PDF