Contextual Info: 08/16/00 Errata: CS8420-CS Rev. D Performance Update Reference CS8420 Data Sheet revision DS245PP2 dated Aug ‘99 1. On page 9 of the data sheet it is specified that in I2C mode, SCL has a maximum rise time of 1µ S and a maximum fall time of 300 nS. The actual rise and fall times should be less than 25 nS.

GEC Plessey Semiconductors

Abstract: SR50D
Contextual Info: THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS DS2454 - 2.1 SR50D 5V PRECISION VOLTAGE REFERENCE The SR50D is a monolithic integrated circuit using the bandgap principle to provide a precise reference voltage of 5V. This reference device is packaged in a standard SOT-23

Contextual Info: DS2450 P R E L IM IN A R Y DALLAS DS2450 W ire Quad A/D Converter SEMICONDUCTOR FEATURES PIN ASSIGNMENT • Four high-impedance inputs to measure analog volt­ ages over the 1-W ire bus • User programmable input range 2.56V, 5.12V , reso­ lution (1 to 16 bits) and alarm thresholds

0A69

Contextual Info: THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS DECEMBER 1992 ADVANCE INFORMATION DS2452 - 2.1 SP5024 1.3 GHz 3-WIRE BUS CONTROLLED SYNTHESISER The SP5024 is a programming variant of the SP5510 allowing the design of one tuner with either I 2C bus or 3-wire

IEC60958

Abstract: CP-1201 IEC-60958 cs8420 AES3 scms CDB8420 CP1201 CS8420-CS sample rate converter
Contextual Info: 8420pi.fm Page -1 Tuesday, October 5, 1999 1:54 PM CS8420 Digital Audio Sample Rate Converter The following information is based on the technical datasheet: CS8420 DS245PP2 AUG’99 Please contact Cirrus Logic for further information. 352'8&7 ,1 250$7,21 Copyright Cirrus Logic, Inc. 1999

SP4902

Abstract: SP5024 SP5024S SP5510 TD6380 2N3904 I2C for TD6381
Contextual Info: SP5024 3-Wire Bus Controlled Synthesiser DS2452 - 2.1 December 1992 The SP5024 is a programming variant of the SP5510 allowing the design of one tuner with either I 2C bus or 3-wire bus format depending on which device is inserted. The SP5024, when used with a TV varicap tuner, forms a complete

Contextual Info: THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS DS2454 - 2.1 SR50D 5V PRECISION VOLTAGE REFERENCE The SR50D is a monolithic integrated circuit using the bandgap principle to provide a precise reference voltage of 5V. This reference device is packaged in a standard SOT-23

DS2450

Abstract: CRC16 DS2450S J-STD-020A afhb
Contextual Info: 1-Wire TM DS2450 Quad A/D Converter www.dalsemi.com FEATURES PIN ASSIGNMENT Four high-impedance inputs to measure analog voltages over the 1-Wire bus User programmable input range 2.56V, 5.12V , resolution (1 to 16 bits) and alarm thresholds 5V, single supply operation

4Mhz crystal

Contextual Info: SP5024 3-Wire Bus Controlled Synthesiser DS2452 - 2.1 December 1992 The SP5024 is a programming variant of the SP5510 allowing the design of one tuner with either I 2C bus or 3-wire bus format depending on which device is inserted. The SP5024, when used with a TV varicap tuner, forms a complete

DS2452

Abstract: 2N3904 SP4902 SP5024 SP5024S SP5510 TD6380 TD6381
Contextual Info: SP5024 3-Wire Bus Controlled Synthesiser DS2452 - 2.1 December 1992 The SP5024 is a programming variant of the SP5510 allowing the design of one tuner with either I 2C bus or 3-wire bus format depending on which device is inserted. The SP5024, when used with a TV varicap tuner, forms a complete

DS2450

Abstract: 12TH CRC16 DS2450S
Contextual Info: DS2450 PRELIMINARY 1–WireTM FEATURES • Four high–impedance inputs to measure analog volt- PIN ASSIGNMENT ages over the 1–Wire bus • User programmable input range 2.56V, 5.12V , reso• • • • • • • • • • • • lution (1 to 16 bits) and alarm thresholds

CRC16

Abstract: DS2450 DS2450S afhb
Contextual Info: DS2450 PRELIMINARY DALLAS SEMICONDUCTOR FEATURES • Four high-impedance inputs to measure analog volt­ ages over the 1-W ire bus • User programmable input range 2.56V, 5.12V , reso­ lution (1 to 16 bits) and alarm thresholds • 5V, single supply operation

Contextual Info: THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS DS2454 - 2.1 SR50D 5V PRECISION VOLTAGE REFERENCE The SR50D is a monolithic integrated circuit using the bandgap principle to provide a precise reference voltage of 5V. This reference device is packaged in a standard SOT-23

DS2452

Contextual Info: THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS DECEMBER 1992 ADVANCE INFORMATION DS2452 - 2.1 SP5024 1.3 GHz 3-WIRE BUS CONTROLLED SYNTHESISER The SP5024 is a programming variant of the SP5510 allowing the design of one tuner with either I 2C bus or 3-wire

Contextual Info: DS2450 PRELIMINARY D A L L A S s e m ic o n d u c t o r FEATURES DS2450 1—W ire Quad A/D Converter PIN ASSIGNMENT • F ourhigh-im pedance inputs to m easure analog volt­ ages o v e rth e 1 -W ire bus VCC QE • User programmable input range 2.56V, 5.12V , reso­

DS2450

Abstract: Logic 5563 TM CRC16 DS2450S
Contextual Info: TM 1-Wire DS2450 Quad A/D Converter www.dalsemi.com FEATURES § Four high-impedance inputs to measure analog voltages over the 1-Wire bus § User programmable input range 2.56V, 5.12V , resolution (1 to 16 bits) and alarm thresholds § 5V, single supply operation

Contextual Info: DECEMBER 1992 ADVANCE INFORMATION DS2452 - 2.1 SP5024 1.3 GHz 3-WIRE BUS CONTROLLED SYNTHESISER The SP5024 is a programming variant of the SP5510 allowing the design of one tuner with either I 2C bus or 3-wire bus format depending on which device is inserted. The

Contextual Info: LE AVAILAB DS2450 1-Wire Quad A/D Converter FEATURES ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ Four high-impedance inputs to measure analog voltages over the 1-Wire bus User programmable input range 2.56V, 5.12V , resolution (1 to 16 bits) and alarm thresholds

Contextual Info: 07/07/99 Errata: CS8420-CS Rev. B Performance Update Reference CS8420 Data Sheet revision DS245PP1 dated Oct ‘98 In this text ‘register’ refers to the control port register file described on pages 27-40 of the datasheet. 1. Performance characteristics are specified with VA and VD at 5V plus or minus 5%.

Contextual Info: LE AVAILAB DS2450 1-Wire Quad A/D Converter FEATURES ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ Four high-impedance inputs to measure analog voltages over the 1-Wire bus User programmable input range 2.56V, 5.12V , resolution (1 to 16 bits) and alarm thresholds

PPMD

Contextual Info: GEC P L E S S E Y ADVANCE INFORMATION [ s e m i c o n d u c t o r s | DS2452 2.1 SP5024 1.3 GHz 3-WIRE BUS CONTROLLED SYNTHESISER Supersedes edition in the Consum er 1C Handbook, September 1991 The SP5024 is a programming variant of the SP5510 allowing the design of one tuner with either l2C bus or 3wire bus format depending on which device is inserted. The

pulse shaping FILTER implementation xilinx

Abstract: xilinx logicore core dds FIR FILTER implementation xilinx structure interpolation CIC Filter CIC interpolation Filter DS245 XIP161 XIP162 area efficient fir filter Polyphase Filter Banks
Contextual Info: MAC FIR v3.0 DS245 v1.5 March 28, 2003 Features • • • • • Drop-in module for Virtex , Virtex-E, Virtex-II, Virtex-II Pro™, Spartan™-II, Spartan-IIE and Spartan-3 FPGAs High-performance single-rate finite impulse response (FIR), polyphase decimator and interpolator

MSBH

Contextual Info: DS2450 1-Wire Quad A/D Converter www.maxim-ic.com FEATURES § § § § § § § § § § § § § § PIN ASSIGNMENT Four high-impedance inputs to measure analog voltages over the 1-WireÒ bus User programmable input range 2.56V, 5.12V , resolution (1 to 16 bits) and alarm

Contextual Info: S i GEC PLESSEY S E M I C O N Ü U ADVANCE INFORMATION T O R S DS2452 - 2.1 SP5024 1.3 GHz 3-WIRE BUS CONTROLLED SYNTHESISER The SP5024 is a programming variant of the SP5510 allowing the design of one tuner with either l2C bus or 3-wire bus format depending on which device is inserted. The