AX12
Abstract: eds2508adt
Text: PRELIMINARY DATA SHEET 256M bits SDRAM EDS2508ADTA 32M words x 8 bits Pin Configurations The EDS2508ADTA is 256M bits SDRAMs organized as 8,388,608 words × 8 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock.
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Original
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PDF
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EDS2508ADTA
EDS2508ADTA
54-pin
133MHz
M01E0107
E0633E10
AX12
eds2508adt
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Untitled
Abstract: No abstract text available
Text: PRELIMINARY DATA SHEET 256M bits SDRAM EDS2508ADTA 32M words x 8 bits Description Pin Configurations The EDS2508ADTA is 256M bits SDRAMs organized as 8,388,608 words × 8 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the
|
Original
|
PDF
|
EDS2508ADTA
EDS2508ADTA
54-pin
133MHz
M01E0107
E0633E10
|