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Texas Instruments EP1830-20CFN IC,COMPLEX-EPLD,48-CELL,47NS PROP DELAY,LDCC,68PIN,PLASTIC
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EP18302 Datasheets (2)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
EP1830-20		Altera	High-Performance 48-Macrocell Devices		Scan	PDF
EP1830-25		Altera	High-Performance 48-Macrocell Devices		Scan	PDF

EP18302 Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
Untitled Abstract: No abstract text available Text: c D -ifn n c c R ic c HIGH-PERFORMANCE 48-MACROCELL ONE-TIME PROGRAMMABLE LOGIC DEVICES S R E S 003-D 3880, NOVEMBER 1991 FN PACKAGE User-Configurable LSI Circuit Capable of Implementing 2100 Equivalent Gates of Conventional and Custom Logic TOP VIEW High-Performance CMOS Process Allows:	OCR Scan	48-MACROCELL 003-D SRES003-D3880.	PDF
Altera EP1810 Abstract: No abstract text available Text: ALTERA CORP 47E D • 05*15372 DQ0211b 376 ■ ALT T ^ to -o / EP1810 EPLD s A N b [m □ □ □ □ □ □ □ □ □ □ High-density replacement for TTL and 74HC High-performance 48-macrocell EPLD with tPD = 20 ns and counter frequencies up to 50 MHz	OCR Scan	000211b EP1810 48-Macrocell EP1830-20, EP1830-25, EP1830-30 EP1830-25 EP1830 Altera EP1810	PDF
Untitled Abstract: No abstract text available Text: EP1830 EPLD Features □ □ General Description Altera's EP1830 Erasable Programmable Logic Device EPLD is a fast, low-power version of the EP1810 device. The EP1830 can implement four 12-bit counters at up to 50 MHz and typically consumes 20 mA when operating at 1 MHz. The EP1830 EPLD is available in OTP plastic 68-pin	OCR Scan	EP1830 EP1810 12-bit 68-pin EP1830-20, EP1830-25,	PDF
components combinational logic circuit Abstract: EP18M-30C EP1830-25CFN 48-MACROCELL Text: C D Itü U t C C D IC Q HIGH-PERFORMANCE 48-MACROCELL ONE-TIME PROGRAMMABLE LOGIC DEVICES S R E S 0 0 3-D 38 8 0, N O V EM BE R 1991 User-Configurable LSI Circuit Capable of Implementing 2100 Equivalent Gates of Conventional and Custom Logic High-Performance CMOS Process Allows:	OCR Scan	EP1830 48-MACROCELL SRES003-D3880. S6S303 components combinational logic circuit EP18M-30C EP1830-25CFN	PDF
EP1830 Abstract: EP1810 jedec 74HC EP1810 EP18302 EP1830 jedec Text: EP1810 EPLDs High-Performance 48-Macrocell Devices Data Sheet September 1991, ver. 2 Features □ □ □ □ □ □ □ Q General Description The EP1810 Erasable Programmable Logic Devices EPLDs offer LSI density,TTL-equivalentspeed, and low power consumption. Each EPLD can	OCR Scan	EP1810 48-Macrocell EP1830-20, EP1830-25, EP1830-30 EP1830-25 EP1830 EP1810 jedec 74HC EP18302 EP1830 jedec	PDF
Untitled Abstract: No abstract text available Text: EP1830 EPLD Features J J IJ □ General Description A ltera's EP1830 Erasable P rog ram m able Logic D ev ice E P L D is a fast, low -p ow er version of the EP1810 device. The EP1830 c an im p lem e n t four 12-bit cou nters at up to 50 M H z and typically co n s u m e s 20 m A w h en	OCR Scan	EP1830 P1810T EP1830-20, EP1830-25, EP1830-30 EP1830-25	PDF